ubsan: xtensa: left shift cannot be represented in type 'int'

[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c

diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index ba33152d5ea4e3406aeff7fdadf22141170d94eb..811509fa1abb180d5be4cb1bc6192e93b42260be 100644 (file)
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble ADI Blackfin Instructions.
-   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+   Copyright (C) 2005-2019 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
 
@@ -38,14 +38,14 @@ typedef long TIword;
 #define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
 
-#include "dis-asm.h"
+#include "disassemble.h"
 
 typedef unsigned int bu32;
 
 struct private
 {
   TIword iw0;
-  int comment, parallel;
+  bfd_boolean comment, parallel;
 };
 
 typedef enum
@@ -167,7 +167,7 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
   else
     {
       if (constant_formats[cf].issigned && x < 0)
-       sprintf (buf, "-0x%x", abs (x));
+       sprintf (buf, "-0x%lx", (unsigned long)(- x));
       else
        sprintf (buf, "0x%lx", (unsigned long) x);
     }
@@ -350,7 +350,7 @@ static const enum machine_registers decode_gregs[] =
   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
 };
 
-#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
+#define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
 
 /* [dregs pregs (iregs mregs) (bregs lregs)].  */
 static const enum machine_registers decode_regs[] =
@@ -361,7 +361,7 @@ static const enum machine_registers decode_regs[] =
   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
 };
 
-#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
+#define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
 
 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
 static const enum machine_registers decode_regs_lo[] =
@@ -372,7 +372,7 @@ static const enum machine_registers decode_regs_lo[] =
   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
 };
 
-#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
+#define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
 
 /* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
 static const enum machine_registers decode_regs_hi[] =
@@ -383,7 +383,7 @@ static const enum machine_registers decode_regs_hi[] =
   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
 };
 
-#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
+#define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
 
 static const enum machine_registers decode_statbits[] =
 {
@@ -1569,7 +1569,7 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ");\t\t/* bit");
       OUTS (outf, imm7d (src));
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (opc == 1)
     {
@@ -1580,7 +1580,7 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ");\t\t/* bit");
       OUTS (outf, imm7d (src));
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (opc == 2)
     {
@@ -1591,7 +1591,7 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ");\t\t/* bit");
       OUTS (outf, imm7d (src));
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (opc == 3)
     {
@@ -1602,7 +1602,7 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ");\t\t/* bit");
       OUTS (outf, imm7d (src));
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (opc == 4)
     {
@@ -1613,7 +1613,7 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ");\t\t/* bit");
       OUTS (outf, imm7d (src));
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (opc == 5)
     {
@@ -1771,7 +1771,7 @@ decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, "(");
       OUTS (outf, imm32 (*pval));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (op == 1)
     {
@@ -1781,7 +1781,7 @@ decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ";\t\t/* (");
       OUTS (outf, imm7d (src));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else
     return 0;
@@ -1827,7 +1827,7 @@ decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, "(");
       OUTS (outf, imm32 (*pval));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (op == 1)
     {
@@ -1837,7 +1837,7 @@ decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, ";\t\t/* (");
       OUTS (outf, imm7d (src));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else
     return 0;
@@ -2043,7 +2043,7 @@ decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
       else if (op == 2 || op == 3)
        OUTS (outf, "4");
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
 
   return 2;
@@ -2743,7 +2743,7 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
        }
 
       OUTS (outf, " */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   if (S == 1 || Z == 1)
     {
@@ -2754,7 +2754,7 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, "(");
       OUTS (outf, imm32 (*pval));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   return 4;
 }
@@ -2919,7 +2919,7 @@ decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, ";\t\t/* (");
       OUTS (outf, uimm16s4d (framesize));
       OUTS (outf, ") */");
-      priv->comment = 1;
+      priv->comment = TRUE;
     }
   else if (R == 1)
     OUTS (outf, "UNLINK");
@@ -4664,7 +4664,7 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
     return -1;
   priv->iw0 = iw0;
 
-  if ((iw0 & 0xc000) == 0xc000)
+  if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
     {
       /* 32-bit insn.  */
       if (ifetch (pc + 2, outf, &iw1))
@@ -4771,8 +4771,8 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
   struct private priv;
   int count;
 
-  priv.parallel = 0;
-  priv.comment = 0;
+  priv.parallel = FALSE;
+  priv.comment = FALSE;
   outf->private_data = &priv;
 
   count = _print_insn_bfin (pc, outf);
@@ -4784,29 +4784,29 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
   if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
       && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
     {
-      int legal = 1;
+      bfd_boolean legal = TRUE;
       int len;
 
-      priv.parallel = 1;
+      priv.parallel = TRUE;
       OUTS (outf, " || ");
       len = _print_insn_bfin (pc + 4, outf);
       if (len == -1)
        return -1;
       OUTS (outf, " || ");
       if (len != 2)
-       legal = 0;
+       legal = FALSE;
       len = _print_insn_bfin (pc + 6, outf);
       if (len == -1)
        return -1;
       if (len != 2)
-       legal = 0;
+       legal = FALSE;
 
       if (legal)
        count = 8;
       else
        {
          OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
-         priv.comment = 1;
+         priv.comment = TRUE;
          count = 0;
        }
     }