/* Disassemble ADI Blackfin Instructions.
- Copyright (C) 2005-2014 Free Software Foundation, Inc.
+ Copyright (C) 2005-2019 Free Software Foundation, Inc.
This file is part of libopcodes.
#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
-#include "dis-asm.h"
+#include "disassemble.h"
typedef unsigned int bu32;
struct private
{
TIword iw0;
- int comment, parallel;
+ bfd_boolean comment, parallel;
};
typedef enum
else
{
if (constant_formats[cf].issigned && x < 0)
- sprintf (buf, "-0x%x", abs (x));
+ sprintf (buf, "-0x%lx", (unsigned long)(- x));
else
sprintf (buf, "0x%lx", (unsigned long) x);
}
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
-#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
+#define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
/* [dregs pregs (iregs mregs) (bregs lregs)]. */
static const enum machine_registers decode_regs[] =
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
};
-#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
+#define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
static const enum machine_registers decode_regs_lo[] =
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
};
-#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
+#define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
static const enum machine_registers decode_regs_hi[] =
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
};
-#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
+#define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
static const enum machine_registers decode_statbits[] =
{
#ifndef OUTS
#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
#endif
+#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
static void
amod0 (int s0, int x0, disassemble_info *outf)
int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
const char *bitname = statbits (cbit);
+ const char * const op_names[] = { "", "|", "&", "^" } ;
if (priv->parallel)
return 0;
bitname = bitnames;
}
- if (op == 0 && D == 0)
- {
- OUTS (outf, "CC = ");
- OUTS (outf, bitname);
- }
- else if (op == 1 && D == 0)
- {
- OUTS (outf, "CC |= ");
- OUTS (outf, bitname);
- }
- else if (op == 2 && D == 0)
- {
- OUTS (outf, "CC &= ");
- OUTS (outf, bitname);
- }
- else if (op == 3 && D == 0)
- {
- OUTS (outf, "CC ^= ");
- OUTS (outf, bitname);
- }
- else if (op == 0 && D == 1)
- {
- OUTS (outf, bitname);
- OUTS (outf, " = CC");
- }
- else if (op == 1 && D == 1)
- {
- OUTS (outf, bitname);
- OUTS (outf, " |= CC");
- }
- else if (op == 2 && D == 1)
- {
- OUTS (outf, bitname);
- OUTS (outf, " &= CC");
- }
- else if (op == 3 && D == 1)
- {
- OUTS (outf, bitname);
- OUTS (outf, " ^= CC");
- }
+ if (D == 0)
+ OUT (outf, "CC %s= %s", op_names[op], bitname);
else
- return 0;
+ OUT (outf, "%s %s= CC", bitname, op_names[op]);
return 2;
}
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (opc == 1)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (opc == 2)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (opc == 3)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (opc == 4)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (opc == 5)
{
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (op == 1)
{
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else
return 0;
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (op == 1)
{
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else
return 0;
else if (op == 2 || op == 3)
OUTS (outf, "4");
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
return 2;
}
OUTS (outf, " */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
if (S == 1 || Z == 1)
{
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
return 4;
}
OUTS (outf, ";\t\t/* (");
OUTS (outf, uimm16s4d (framesize));
OUTS (outf, ") */");
- priv->comment = 1;
+ priv->comment = TRUE;
}
else if (R == 1)
OUTS (outf, "UNLINK");
return -1;
priv->iw0 = iw0;
- if ((iw0 & 0xc000) == 0xc000)
+ if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
{
/* 32-bit insn. */
if (ifetch (pc + 2, outf, &iw1))
struct private priv;
int count;
- priv.parallel = 0;
- priv.comment = 0;
+ priv.parallel = FALSE;
+ priv.comment = FALSE;
outf->private_data = &priv;
count = _print_insn_bfin (pc, outf);
if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
&& ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
{
- int legal = 1;
+ bfd_boolean legal = TRUE;
int len;
- priv.parallel = 1;
+ priv.parallel = TRUE;
OUTS (outf, " || ");
len = _print_insn_bfin (pc + 4, outf);
if (len == -1)
return -1;
OUTS (outf, " || ");
if (len != 2)
- legal = 0;
+ legal = FALSE;
len = _print_insn_bfin (pc + 6, outf);
if (len == -1)
return -1;
if (len != 2)
- legal = 0;
+ legal = FALSE;
if (legal)
count = 8;
else
{
OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
- priv.comment = 1;
+ priv.comment = TRUE;
count = 0;
}
}