/* Disassembler code for CRX.
- Copyright 2004, 2005, 2006, 2007, 2012 Free Software Foundation, Inc.
+ Copyright (C) 2004-2020 Free Software Foundation, Inc.
Contributed by Tomer Levi, NSC, Israel.
Written by Tomer Levi.
MA 02110-1301, USA. */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "opcode/crx.h"
/* String to print when opcode was not matched. */
/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
#define EXTRACT(a, offs, n_bits) \
- (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \
- : (((a) >> (offs)) & ((1 << (n_bits)) -1)))
+ (((a) >> (offs)) & ((2ull << (n_bits - 1)) - 1))
/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */
-#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs)))
+#define SBM(offs) ((-1u << (offs)) & 0xffffffff)
typedef unsigned long dwordU;
typedef unsigned short wordU;
cinv_entry;
/* CRX 'cinv' options. */
-const cinv_entry crx_cinvs[] =
+static const cinv_entry crx_cinvs[] =
{
- {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
- {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
- {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
+ {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
+ {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
+ {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
};
/* CO-Processor register (c<N>). */
COP_ARG,
/* CO-Processor special register (cs<N>). */
- COPS_ARG
+ COPS_ARG
}
REG_ARG_TYPE;
/* Number of valid 'cinv' instruction options. */
-int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
+static int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
/* Current opcode table entry we're disassembling. */
-const inst *instruction;
+static const inst *instruction;
/* Current instruction we're disassembling. */
-ins currInsn;
+static ins currInsn;
/* The current instruction is read into 3 consecutive words. */
-wordU words[3];
+static wordU words[3];
/* Contains all words in appropriate order. */
-ULONGLONG allWords;
+static ULONGLONG allWords;
/* Holds the current processed argument number. */
-int processing_argument_number;
+static int processing_argument_number;
/* Nonzero means a CST4 instruction. */
-int cst4flag;
+static int cst4flag;
/* Nonzero means the instruction's original size is
incremented (escape sequence is used). */
-int size_changed;
-
-static int get_number_of_operands (void);
-static argtype getargtype (operand_type);
-static int getbits (operand_type);
-static char *getregname (reg);
-static char *getcopregname (copreg, reg_type);
-static char * getprocregname (int);
-static char *gettrapstring (unsigned);
-static char *getcinvstring (unsigned);
-static void getregliststring (int, char *, enum REG_ARG_TYPE);
-static wordU get_word_at_PC (bfd_vma, struct disassemble_info *);
-static void get_words_at_PC (bfd_vma, struct disassemble_info *);
-static unsigned long build_mask (void);
-static int powerof2 (int);
-static int match_opcode (void);
-static void make_instruction (void);
-static void print_arguments (ins *, bfd_vma, struct disassemble_info *);
-static void print_arg (argument *, bfd_vma, struct disassemble_info *);
+static int size_changed;
+
/* Retrieve the number of operands for the current assembled instruction. */
{
int i;
- for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+ for (i = 0; i < MAX_OPERANDS && instruction->operands[i].op_type; i++)
;
return i;
/* Given a register enum value, retrieve its name. */
-char *
+static char *
getregname (reg r)
{
const reg_entry * regentry = &crx_regtab[r];
/* Given a coprocessor register enum value, retrieve its name. */
-char *
+static char *
getcopregname (copreg r, reg_type type)
{
const reg_entry * regentry;
/* Transform a register bit mask to a register list. */
-void
+static void
getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
{
- char temp_string[5];
+ char temp_string[16];
int i;
string[0] = '{';
/* Build a mask of the instruction's 'constant' opcode,
based on the instruction's printing flags. */
-static unsigned long
+static unsigned int
build_mask (void)
{
unsigned int print_flags;
- unsigned long mask;
+ unsigned int mask;
print_flags = instruction->flags & FMT_CRX;
switch (print_flags)
static int
match_opcode (void)
{
- unsigned long mask;
+ unsigned int mask;
/* The instruction 'constant' opcode doewsn't exceed 32 bits. */
- unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
+ unsigned int doubleWord = words[1] + ((unsigned) words[0] << 16);
/* Start searching from end of instruction table. */
instruction = &crx_instruction[NUMOPCODES - 2];
else if (INST_HAS_REG_LIST)
{
- REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
- COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
+ REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
+ COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
COPS_ARG : (instruction->flags & USER_REG) ?
USER_REG_ARG : REG_ARG;
/* Prints the instruction by calling print_arguments after proper matching. */
int
-print_insn_crx (memaddr, info)
- bfd_vma memaddr;
- struct disassemble_info *info;
+print_insn_crx (bfd_vma memaddr, struct disassemble_info *info)
{
int is_decoded; /* Nonzero means instruction has a match. */
/* Find a matching opcode in table. */
is_decoded = match_opcode ();
/* If found, print the instruction's mnemonic and arguments. */
- if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0)
+ if (is_decoded > 0 && (words[0] != 0 || words[1] != 0))
{
info->fprintf_func (info->stream, "%s", instruction->mnemonic);
if ((currInsn.nargs = get_number_of_operands ()) != 0)
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