/* This processor in fact is little endian. The value set here
reflects the way opcodes are written in the cgen description. */
info->endian = BFD_ENDIAN_BIG;
- if (! info->insn_sets)
+ if (!info->private_data)
{
- info->insn_sets = cgen_bitset_create (ISA_MAX);
+ info->private_data = cgen_bitset_create (ISA_MAX);
if (info->mach == bfd_mach_m16c)
- cgen_bitset_set (info->insn_sets, ISA_M16C);
+ cgen_bitset_set (info->private_data, ISA_M16C);
else
- cgen_bitset_set (info->insn_sets, ISA_M32C);
+ cgen_bitset_set (info->private_data, ISA_M32C);
}
break;
#endif
#ifdef ARCH_bpf
case bfd_arch_bpf:
- if (!info->insn_sets)
- {
- info->insn_sets = cgen_bitset_create (ISA_EBPFMAX);
- if (info->endian == BFD_ENDIAN_BIG)
- cgen_bitset_set (info->insn_sets, ISA_EBPFBE);
- else
- cgen_bitset_set (info->insn_sets, ISA_EBPFLE);
- }
+ if (!info->private_data)
+ {
+ info->private_data = cgen_bitset_create (ISA_EBPFMAX);
+ if (info->endian == BFD_ENDIAN_BIG)
+ cgen_bitset_set (info->private_data, ISA_EBPFBE);
+ else
+ cgen_bitset_set (info->private_data, ISA_EBPFLE);
+ }
break;
#endif
#ifdef ARCH_pru
}
}
+void
+disassemble_free_target (struct disassemble_info *info)
+{
+ if (info == NULL)
+ return;
+
+ switch (info->arch)
+ {
+ default:
+ return;
+
+#ifdef ARCH_bpf
+ case bfd_arch_bpf:
+#endif
+#ifdef ARCH_m32c
+ case bfd_arch_m32c:
+#endif
+#if defined ARCH_bpf || defined ARCH_m32c
+ if (info->private_data)
+ {
+ CGEN_BITSET *mask = info->private_data;
+ free (mask->bits);
+ }
+ break;
+#endif
+
+#ifdef ARCH_arc
+ case bfd_arch_arc:
+ break;
+#endif
+#ifdef ARCH_cris
+ case bfd_arch_cris:
+ break;
+#endif
+#ifdef ARCH_mmix
+ case bfd_arch_mmix:
+ break;
+#endif
+#ifdef ARCH_nfp
+ case bfd_arch_nfp:
+ break;
+#endif
+#ifdef ARCH_powerpc
+ case bfd_arch_powerpc:
+ break;
+#endif
+#ifdef ARCH_riscv
+ case bfd_arch_riscv:
+ break;
+#endif
+#ifdef ARCH_rs6000
+ case bfd_arch_rs6000:
+ break;
+#endif
+ }
+
+ free (info->private_data);
+}
+
/* Remove whitespace and consecutive commas from OPTIONS. */
char *