ubsan: aarch64: left shift cannot be represented in type 'int64_t'

[deliverable/binutils-gdb.git] / opcodes / dlx-dis.c

diff --git a/opcodes/dlx-dis.c b/opcodes/dlx-dis.c
index 9e9a83dbf938472d5990335d197fd0184e8e978d..c6b6d33d800dd6ef44d1f145979f2e83f434cdbe 100644 (file)
--- a/opcodes/dlx-dis.c
+++ b/opcodes/dlx-dis.c
@@ -1,16 +1,18 @@
 /* Instruction printing code for the DLX Microprocessor
-   Copyright 2002, 2005 Free Software Foundation, Inc.
+   Copyright (C) 2002-2019 Free Software Foundation, Inc.
    Contributed by Kuang Hwa Lin.  Written by Kuang Hwa Lin, 03/2002.
 
-   This program is free software; you can redistribute it and/or modify
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
@@ -18,7 +20,7 @@
    MA 02110-1301, USA.  */
 
 #include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "opcode/dlx.h"
 
 #define R_ERROR     0x1
@@ -293,7 +295,7 @@ dlx_aluI_type (struct disassemble_info* info)
     { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
     { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
     { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
-#if 0                                                 
+#if 0
     { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
     { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
 #endif
@@ -435,19 +437,18 @@ print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
   bfd_byte buffer[4];
   int insn_idx;
   unsigned long insn_word;
-  unsigned char rtn_code;
-  unsigned long dlx_insn_type[] =
+  dlx_insn dlx_insn_type[] =
   {
-    (unsigned long) dlx_r_type,
-    (unsigned long) dlx_load_type,
-    (unsigned long) dlx_store_type,
-    (unsigned long) dlx_aluI_type,
-    (unsigned long) dlx_br_type,
-    (unsigned long) dlx_jmp_type,
-    (unsigned long) dlx_jr_type,
-    (unsigned long) NULL
+    dlx_r_type,
+    dlx_load_type,
+    dlx_store_type,
+    dlx_aluI_type,
+    dlx_br_type,
+    dlx_jmp_type,
+    dlx_jr_type,
+    (dlx_insn) NULL
   };
-  int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
+  int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1;
   int status =
     (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);
 
@@ -479,11 +480,10 @@ print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
 #endif
 
   /* Scan through all the insn type and print the insn out.  */
-  rtn_code = 0;
   current_insn_addr = (unsigned long) memaddr;
 
   for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
-    switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info))
+    switch ((dlx_insn_type[insn_idx]) (info))
       {
        /* Found the correct opcode   */
       case R_TYPE: