#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
-#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
- /* XMM register or double/quad word memory operand, depending on
- VEX.W. */
- xmm_mdq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
vex128_mode,
/* 256bit vex mode */
vex256_mode,
- /* operand size depends on the VEX.W bit. */
- vex_w_dq_mode,
- /* Similar to vex_w_dq_mode, with VSIB dword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
- /* Similar to vex_w_dq_mode, with VSIB qword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
- /* like vex_w_dq_mode, ignore vector length. */
+ /* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
/* Static rounding. */
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_3_RM_1,
PREFIX_0F01_REG_5_MOD_0,
PREFIX_0F01_REG_5_MOD_3_RM_0,
PREFIX_0F01_REG_5_MOD_3_RM_2,
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0D,
+ X86_64_0E,
X86_64_16,
X86_64_17,
X86_64_1E,
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w' or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
+ '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
+ prefix or suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0D) },
+ { X86_64_TABLE (X86_64_0E) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw, BND }, 0 },
- { "retT", { BND }, 0 },
+ { X86_64_TABLE (X86_64_C2) },
+ { X86_64_TABLE (X86_64_C3) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_3_MOD_1 */
+ {
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
{ "popP", { es }, 0 },
},
- /* X86_64_0D */
+ /* X86_64_0E */
{
{ "pushP", { cs }, 0 },
},
{ "Jcall{T|}", { Ap }, 0 },
},
+ /* X86_64_C2 */
+ {
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
+ },
+
+ /* X86_64_C3 */
+ {
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
+ },
+
/* X86_64_C4 */
{
{ MOD_TABLE (MOD_C4_32BIT) },
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
- { "vmmcall", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
case 'B':
if (l == 0 && len == 1)
{
-case_B:
+ case_B:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
SAVE_LAST (*p);
break;
}
-case_L:
+ case_L:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
case 'P':
if (l == 0 && len == 1)
{
-case_P:
+ case_P:
if (intel_syntax)
{
if ((rex & REX_W) == 0
case 'Q':
if (l == 0 && len == 1)
{
-case_Q:
+ case_Q:
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
case 'S':
if (l == 0 && len == 1)
{
-case_S:
+ case_S:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
case '^':
if (intel_syntax)
break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
case o_mode:
oappend ("OWORD PTR ");
break;
- case xmm_mdq_mode:
- case vex_w_dq_mode:
case vex_scalar_w_dq_mode:
if (!need_vex)
abort ();
break;
}
/* fall through */
+ case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
- case xmm_mdq_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
}
if ((havebase || haveindex || needindex || needaddr32 || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != v_bndmk_mode)
- && (bytemode != bnd_mode)
- && (bytemode != bnd_swap_mode))
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
}
}
}
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
else
{
/* 16 bit address mode */
&& bytemode != xmm_mw_mode
&& bytemode != xmm_md_mode
&& bytemode != xmm_mq_mode
- && bytemode != xmm_mdq_mode
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
if (modrm.mod == 3)
{
int add;
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
OP_M (bytemode, sizeflag);
}
break;
}
-skip:
+ skip:
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
projects / deliverable / binutils-gdb.git / blobdiff