/* Print i386 instructions for GDB, the GNU debugger.
- Copyright (C) 1988-2019 Free Software Foundation, Inc.
+ Copyright (C) 1988-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
-static void OP_Mwaitx (int, int);
static void NOP_Fixup1 (int, int);
static void NOP_Fixup2 (int, int);
static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
+static void SEP_Fixup (int, int);
static void BND_Fixup (int, int);
static void NOTRACK_Fixup (int, int);
static void HLE_Fixup1 (int, int);
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define Iv { OP_I, v_mode }
#define sIv { OP_sI, v_mode }
-#define Iq { OP_I, q_mode }
#define Iv64 { OP_I64, v_mode }
+#define Id { OP_I, d_mode }
#define Iw { OP_I, w_mode }
#define I1 { OP_I, const_1_mode }
#define Jb { OP_J, b_mode }
#define Jv { OP_J, v_mode }
+#define Jdqw { OP_J, dqw_mode }
#define Cm { OP_C, m_mode }
#define Dm { OP_D, m_mode }
#define Td { OP_T, d_mode }
#define EXd { OP_EX, d_mode }
#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
-#define EXdScalarS { OP_EX, d_scalar_swap_mode }
#define EXq { OP_EX, q_mode }
#define EXqScalar { OP_EX, q_scalar_mode }
#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EMCq { OP_EMC, q_mode }
#define MXC { OP_MXC, 0 }
#define OPSUF { OP_3DNowSuffix, 0 }
+#define SEP { SEP_Fixup, 0 }
#define CMP { CMP_Fixup, 0 }
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
#define Vex128 { OP_VEX, vex128_mode }
#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
-#define EXdVex { OP_EX_Vex, d_mode }
-#define EXdVexS { OP_EX_Vex, d_swap_mode }
#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
-#define EXqVex { OP_EX_Vex, q_mode }
-#define EXqVexS { OP_EX_Vex, q_swap_mode }
#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
#define EXVexW { OP_EX_VexW, x_mode }
#define EXdVexW { OP_EX_VexW, d_mode }
#define EXqVexW { OP_EX_VexW, q_mode }
#define EXVexImmW { OP_EX_VexImmW, x_mode }
-#define XMVex { OP_XMM_Vex, 0 }
#define XMVexScalar { OP_XMM_Vex, scalar_mode }
#define XMVexW { OP_XMM_VexW, 0 }
#define XMVexI4 { OP_REG_VexI4, x_mode }
v_bndmk_mode,
/* operand size depends on REX prefixes. */
dq_mode,
- /* registers like dq_mode, memory like w_mode. */
+ /* registers like dq_mode, memory like w_mode, displacements like
+ v_mode without considering Intel64 ISA. */
dqw_mode,
/* bounds operand */
bnd_mode,
REG_0F01,
REG_0F0D,
REG_0F18,
- REG_0F1C_MOD_0,
- REG_0F1E_MOD_3,
+ REG_0F1C_P_0_MOD_0,
+ REG_0F1E_P_1_MOD_3,
REG_0F71,
REG_0F72,
REG_0F73,
MOD_VEX_W_0_0F3A33_P_2_LEN_0,
MOD_VEX_W_1_0F3A33_P_2_LEN_0,
- MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3,
- MOD_EVEX_0F11_PREFIX_1,
- MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0,
MOD_EVEX_0F16_PREFIX_0,
MOD_EVEX_0F38C6_REG_1,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
- RM_0F01_REG_5,
- RM_0F01_REG_7,
- RM_0F1E_MOD_3_REG_7,
- RM_0FAE_REG_6,
- RM_0FAE_REG_7
+ RM_0F01_REG_5_MOD_3,
+ RM_0F01_REG_7_MOD_3,
+ RM_0F1E_P_1_MOD_3_REG_7,
+ RM_0FAE_REG_6_MOD_3_P_0,
+ RM_0FAE_REG_7_MOD_3,
};
enum
{
PREFIX_90 = 0,
- PREFIX_MOD_0_0F01_REG_5,
- PREFIX_MOD_3_0F01_REG_5_RM_0,
- PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F01_REG_5_MOD_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_3,
PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F7D,
PREFIX_0F7E,
PREFIX_0F7F,
- PREFIX_0FAE_REG_0,
- PREFIX_0FAE_REG_1,
- PREFIX_0FAE_REG_2,
- PREFIX_0FAE_REG_3,
- PREFIX_MOD_0_0FAE_REG_4,
- PREFIX_MOD_3_0FAE_REG_4,
- PREFIX_MOD_0_0FAE_REG_5,
- PREFIX_MOD_3_0FAE_REG_5,
- PREFIX_MOD_0_0FAE_REG_6,
- PREFIX_MOD_1_0FAE_REG_6,
- PREFIX_0FAE_REG_7,
+ PREFIX_0FAE_REG_0_MOD_3,
+ PREFIX_0FAE_REG_1_MOD_3,
+ PREFIX_0FAE_REG_2_MOD_3,
+ PREFIX_0FAE_REG_3_MOD_3,
+ PREFIX_0FAE_REG_4_MOD_0,
+ PREFIX_0FAE_REG_4_MOD_3,
+ PREFIX_0FAE_REG_5_MOD_0,
+ PREFIX_0FAE_REG_5_MOD_3,
+ PREFIX_0FAE_REG_6_MOD_0,
+ PREFIX_0FAE_REG_6_MOD_3,
+ PREFIX_0FAE_REG_7_MOD_0,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
- PREFIX_MOD_0_0FC3,
- PREFIX_MOD_0_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_7,
+ PREFIX_0FC3_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_3,
+ PREFIX_0FC7_REG_7_MOD_3,
PREFIX_0FD0,
PREFIX_0FD6,
PREFIX_0FE6,
VEX_LEN_0F16_P_0_M_1,
VEX_LEN_0F16_P_2,
VEX_LEN_0F17_M_0,
- VEX_LEN_0F2A_P_1,
- VEX_LEN_0F2A_P_3,
- VEX_LEN_0F2C_P_1,
- VEX_LEN_0F2C_P_3,
- VEX_LEN_0F2D_P_1,
- VEX_LEN_0F2D_P_3,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F42_P_0,
EVEX_LEN_0F385A_P_2_W_1,
EVEX_LEN_0F385B_P_2_W_0,
EVEX_LEN_0F385B_P_2_W_1,
+ EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2,
+ EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1,
+ EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1,
+ EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1,
+ EVEX_LEN_0F38C7_R_6_P_2_W_0,
+ EVEX_LEN_0F38C7_R_6_P_2_W_1,
EVEX_LEN_0F3A18_P_2_W_0,
EVEX_LEN_0F3A18_P_2_W_1,
EVEX_LEN_0F3A19_P_2_W_0,
VEX_W_0F3ACF_P_2,
EVEX_W_0F10_P_0,
- EVEX_W_0F10_P_1_M_0,
- EVEX_W_0F10_P_1_M_1,
+ EVEX_W_0F10_P_1,
EVEX_W_0F10_P_2,
- EVEX_W_0F10_P_3_M_0,
- EVEX_W_0F10_P_3_M_1,
+ EVEX_W_0F10_P_3,
EVEX_W_0F11_P_0,
- EVEX_W_0F11_P_1_M_0,
- EVEX_W_0F11_P_1_M_1,
+ EVEX_W_0F11_P_1,
EVEX_W_0F11_P_2,
- EVEX_W_0F11_P_3_M_0,
- EVEX_W_0F11_P_3_M_1,
+ EVEX_W_0F11_P_3,
EVEX_W_0F12_P_0_M_0,
EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1,
{ "rdtsc", { XX }, 0 },
{ "rdmsr", { XX }, 0 },
{ "rdpmc", { XX }, 0 },
- { "sysenter", { XX }, 0 },
- { "sysexit", { XX }, 0 },
+ { "sysenter", { SEP }, 0 },
+ { "sysexit", { SEP }, 0 },
{ Bad_Opcode },
{ "getsec", { XX }, 0 },
/* 38 */
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
- /* REG_0F1C_MOD_0 */
+ /* REG_0F1C_P_0_MOD_0 */
{
{ "cldemote", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
},
- /* REG_0F1E_MOD_3 */
+ /* REG_0F1E_P_1_MOD_3 */
{
{ "nopQ", { Ev }, 0 },
{ "rdsspK", { Rdq }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
+ { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
},
/* REG_0F71 */
{
},
/* REG_XOP_LWP */
{
- { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
- { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
+ { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
+ { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
},
/* REG_XOP_TBM_01 */
{
{ Bad_Opcode },
- { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
},
/* REG_XOP_TBM_02 */
{
{ Bad_Opcode },
- { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
},
#include "i386-dis-evex-reg.h"
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
- /* PREFIX_MOD_0_0F01_REG_5 */
+ /* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
{ "rstorssp", { Mq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
+ /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
{
{ Bad_Opcode },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
+ /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
{
{ Bad_Opcode },
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
+ /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
+ {
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mcommit", { Skip_MODRM }, 0 },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
+ {
+ { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 },
+ },
+
/* PREFIX_0F09 */
{
{ "wbinvd", { XX }, 0 },
{ "movdqa", { EXxS, XM }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_0 */
+ /* PREFIX_0FAE_REG_0_MOD_3 */
{
{ Bad_Opcode },
{ "rdfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_1 */
+ /* PREFIX_0FAE_REG_1_MOD_3 */
{
{ Bad_Opcode },
{ "rdgsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_2 */
+ /* PREFIX_0FAE_REG_2_MOD_3 */
{
{ Bad_Opcode },
{ "wrfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_3 */
+ /* PREFIX_0FAE_REG_3_MOD_3 */
{
{ Bad_Opcode },
{ "wrgsbase", { Ev }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_0 */
{
{ "xsave", { FXSAVE }, 0 },
{ "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_MOD_3_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_3 */
{
{ Bad_Opcode },
{ "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_0 */
{
{ "xrstor", { FXSAVE }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_3 */
{
{ "lfence", { Skip_MODRM }, 0 },
{ "incsspK", { Rdq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_0 */
{
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
{ "clwb", { Mb }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_1_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_3 */
{
- { RM_TABLE (RM_0FAE_REG_6) },
+ { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
{ "umonitor", { Eva }, PREFIX_OPCODE },
{ "tpause", { Edq }, PREFIX_OPCODE },
{ "umwait", { Edq }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_7 */
+ /* PREFIX_0FAE_REG_7_MOD_0 */
{
{ "clflush", { Mb }, 0 },
{ Bad_Opcode },
{ "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC3 */
+ /* PREFIX_0FC3_MOD_0 */
{
{ "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_0 */
{
{ "vmptrld",{ Mq }, 0 },
{ "vmxon", { Mq }, 0 },
{ "vmclear",{ Mq }, 0 },
},
- /* PREFIX_MOD_3_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_3 */
{
{ "rdrand", { Ev }, 0 },
{ Bad_Opcode },
{ "rdrand", { Ev }, 0 }
},
- /* PREFIX_MOD_3_0FC7_REG_7 */
+ /* PREFIX_0FC7_REG_7_MOD_3 */
{
{ "rdseed", { Ev }, 0 },
{ "rdpid", { Em }, 0 },
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
+ { "vcvttss2si", { Gdq, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
+ { "vcvttsd2si", { Gdq, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
+ { "vcvtss2si", { Gdq, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
+ { "vcvtsd2si", { Gdq, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F2E */
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { "bextr", { Gv, Ev, Iq }, 0 },
+ { "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
{ "vmovhpX", { EXq, XM }, 0 },
},
- /* VEX_LEN_0F2A_P_1 */
- {
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2A_P_3 */
- {
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_1 */
- {
- { "vcvttss2si", { Gv, EXdScalar }, 0 },
- { "vcvttss2si", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_3 */
- {
- { "vcvttsd2si", { Gv, EXqScalar }, 0 },
- { "vcvttsd2si", { Gv, EXqScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_1 */
- {
- { "vcvtss2si", { Gv, EXdScalar }, 0 },
- { "vcvtss2si", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_3 */
- {
- { "vcvtsd2si", { Gv, EXqScalar }, 0 },
- { "vcvtsd2si", { Gv, EXqScalar }, 0 },
- },
-
/* VEX_LEN_0F41_P_0 */
{
{ Bad_Opcode },
},
{
/* MOD_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
- { RM_TABLE (RM_0F01_REG_5) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
+ { RM_TABLE (RM_0F01_REG_5_MOD_3) },
},
{
/* MOD_0F01_REG_7 */
{ "invlpg", { Mb }, 0 },
- { RM_TABLE (RM_0F01_REG_7) },
+ { RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
/* MOD_0F12_PREFIX_0 */
},
{
/* MOD_0F1C_PREFIX_0 */
- { REG_TABLE (REG_0F1C_MOD_0) },
+ { REG_TABLE (REG_0F1C_P_0_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1E_PREFIX_1 */
{ "nopQ", { Ev }, 0 },
- { REG_TABLE (REG_0F1E_MOD_3) },
+ { REG_TABLE (REG_0F1E_P_1_MOD_3) },
},
{
/* MOD_0F24 */
{
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
},
{
/* MOD_0FAE_REG_1 */
{ "fxrstor", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
},
{
/* MOD_0FAE_REG_2 */
{ "ldmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
},
{
/* MOD_0FAE_REG_3 */
{ "stmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
},
{
/* MOD_0FAE_REG_4 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
},
{
/* MOD_0FAE_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
},
{
/* MOD_0FAE_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
},
{
/* MOD_0FAE_REG_7 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
- { RM_TABLE (RM_0FAE_REG_7) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
+ { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
},
{
/* MOD_0FB2 */
},
{
/* MOD_0FC3 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
},
{
/* MOD_0FC7_REG_3 */
},
{
/* MOD_0FC7_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
},
{
/* MOD_0FC7_REG_7 */
{ "vmptrst", { Mq }, 0 },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
{
/* MOD_0FD7 */
},
{
/* MOD_0F38F9_PREFIX_0 */
- { "movdiri", { Em, Gv }, PREFIX_OPCODE },
+ { "movdiri", { Ev, Gv }, PREFIX_OPCODE },
},
{
/* MOD_62_32BIT */
},
{
/* RM_C7_REG_7 */
- { "xbeginT", { Skip_MODRM, Jv }, 0 },
+ { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
},
{
/* RM_0F01_REG_0 */
{ "invlpga", { Skip_MODRM }, 0 },
},
{
- /* RM_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
+ /* RM_0F01_REG_5_MOD_3 */
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "wrpkru", { Skip_MODRM }, 0 },
},
{
- /* RM_0F01_REG_7 */
+ /* RM_0F01_REG_7_MOD_3 */
{ "swapgs", { Skip_MODRM }, 0 },
{ "rdtscp", { Skip_MODRM }, 0 },
- { "monitorx", { { OP_Monitor, 0 } }, 0 },
- { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
{ "clzero", { Skip_MODRM }, 0 },
+ { "rdpru", { Skip_MODRM }, 0 },
},
{
- /* RM_0F1E_MOD_3_REG_7 */
+ /* RM_0F1E_P_1_MOD_3_REG_7 */
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
},
{
- /* RM_0FAE_REG_6 */
+ /* RM_0FAE_REG_6_MOD_3 */
{ "mfence", { Skip_MODRM }, 0 },
},
{
- /* RM_0FAE_REG_7 */
+ /* RM_0FAE_REG_7_MOD_3 */
{ "sfence", { Skip_MODRM }, 0 },
},
enum x86_64_isa
{
- amd64 = 0,
+ amd64 = 1,
intel64
};
}
}
- if ((havebase || haveindex || needaddr32 || riprel)
+ if ((havebase || haveindex || needindex || needaddr32 || riprel)
&& (bytemode != v_bnd_mode)
&& (bytemode != v_bndmk_mode)
&& (bytemode != bnd_mode)
op = *codep++;
mask = 0xff;
break;
- case q_mode:
- if (address_mode == mode_64bit)
- {
- op = get32s ();
- break;
- }
- /* Fall through. */
case v_mode:
USED_REX (REX_W);
if (rex & REX_W)
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case d_mode:
+ mask = 0xffffffff;
+ op = get32 ();
+ break;
case w_mode:
mask = 0xfffff;
op = get16 ();
disp -= 0x100;
break;
case v_mode:
- if (isa64 == amd64)
+ if (isa64 != intel64)
+ case dqw_mode:
USED_REX (REX_W);
if ((sizeflag & DFLAG)
|| (address_mode == mode_64bit
- && (isa64 != amd64 || (rex & REX_W))))
+ && ((isa64 == intel64 && bytemode != dqw_mode)
+ || (rex & REX_W))))
disp = get32s ();
else
{
& ~((bfd_vma) 0xffff));
}
if (address_mode != mode_64bit
- || (isa64 == amd64 && !(rex & REX_W)))
+ || (isa64 != intel64 && !(rex & REX_W)))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
default:
}
static void
-OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- /* mwaitx %eax,%ecx,%ebx */
+ /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
if (!intel_syntax)
{
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[3]);
- two_source_ops = 1;
- }
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-}
-
-static void
-OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* mwait %eax,%ecx */
- if (!intel_syntax)
- {
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
+ strcpy (op_out[0], names32[0]);
+ strcpy (op_out[1], names32[1]);
+ if (bytemode == eBX_reg)
+ strcpy (op_out[2], names32[3]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
int sizeflag ATTRIBUTE_UNUSED)
{
- /* monitor %eax,%ecx,%edx" */
+ /* monitor %{e,r,}ax,%ecx,%edx" */
if (!intel_syntax)
{
- const char **op1_names;
const char **names = (address_mode == mode_64bit
? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- op1_names = (address_mode == mode_16bit
- ? names16 : names);
- else
+ if (prefixes & PREFIX_ADDR)
{
/* Remove "addr16/addr32". */
all_prefixes[last_addr_prefix] = 0;
- op1_names = (address_mode != mode_32bit
- ? names32 : names16);
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
used_prefixes |= PREFIX_ADDR;
}
- strcpy (op_out[0], op1_names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[2]);
+ else if (address_mode == mode_16bit)
+ names = names16;
+ strcpy (op_out[0], names[0]);
+ strcpy (op_out[1], names32[1]);
+ strcpy (op_out[2], names32[2]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
}
}
+static void
+SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if ( isa64 != amd64 )
+ return;
+
+ obufp = obuf;
+ BadOp ();
+ mnemonicendp = obufp;
+ ++codep;
+}
+
/* For BND-prefixed instructions 0xF2 prefix should be displayed as
"bnd". */
projects / deliverable / binutils-gdb.git / blobdiff