#define Eb { OP_E, b_mode }
#define Ebnd { OP_E, bnd_mode }
#define EbS { OP_E, b_swap_mode }
+#define EbndS { OP_E, bnd_swap_mode }
#define Ev { OP_E, v_mode }
+#define Eva { OP_E, va_mode }
#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
+#define Edqa { OP_E, dqa_mode }
#define Eq { OP_E, q_mode }
#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv_bnd { OP_M, v_bndmk_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
#define Gd { OP_G, d_mode }
#define Gdq { OP_G, dq_mode }
#define Gm { OP_G, m_mode }
+#define Gva { OP_G, va_mode }
#define Gw { OP_G, w_mode }
#define Rd { OP_R, d_mode }
#define Rdq { OP_R, dq_mode }
v_mode,
/* operand size depends on prefixes with operand swapped */
v_swap_mode,
+ /* operand size depends on address prefix */
+ va_mode,
/* word operand */
w_mode,
/* double word operand */
cond_jump_mode,
loop_jcxz_mode,
v_bnd_mode,
+ /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
+ v_bndmk_mode,
/* operand size depends on REX prefixes. */
dq_mode,
/* registers like dq_mode, memory like w_mode. */
dqw_mode,
+ /* bounds operand */
bnd_mode,
+ /* bounds operand with operand swapped */
+ bnd_swap_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
+ /* operand size depends on the W bit as well as address mode. */
+ dqa_mode,
/* normal vex mode */
vex_mode,
/* 128bit vex mode */
REG_0F01,
REG_0F0D,
REG_0F18,
+ REG_0F1C_MOD_0,
REG_0F1E_MOD_3,
REG_0F71,
REG_0F72,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
+ MOD_0F1C_PREFIX_0,
MOD_0F1E_PREFIX_1,
MOD_0F24,
MOD_0F26,
MOD_0F382A_PREFIX_2,
MOD_0F38F5_PREFIX_2,
MOD_0F38F6_PREFIX_0,
+ MOD_0F38F8_PREFIX_2,
+ MOD_0F38F9_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_0,
PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
PREFIX_0F1A,
PREFIX_0F1B,
+ PREFIX_0F1C,
PREFIX_0F1E,
PREFIX_0F2A,
PREFIX_0F2B,
PREFIX_MOD_3_0FAE_REG_4,
PREFIX_MOD_0_0FAE_REG_5,
PREFIX_MOD_3_0FAE_REG_5,
- PREFIX_0FAE_REG_6,
+ PREFIX_MOD_0_0FAE_REG_6,
+ PREFIX_MOD_1_0FAE_REG_6,
PREFIX_0FAE_REG_7,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0F38F1,
PREFIX_0F38F5,
PREFIX_0F38F6,
+ PREFIX_0F38F8,
+ PREFIX_0F38F9,
PREFIX_0F3A08,
PREFIX_0F3A09,
PREFIX_0F3A0A,
prefix and behave as 'S' otherwise
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
- 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
- suffix_always is true.
+ 'Y' unused.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
{ "sysret%LP", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
- { "wbinvd", { XX }, 0 },
+ { PREFIX_TABLE (PREFIX_0F09) },
{ Bad_Opcode },
{ "ud2", { XX }, 0 },
{ Bad_Opcode },
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F1A) },
{ PREFIX_TABLE (PREFIX_0F1B) },
- { "nopQ", { Ev }, 0 },
+ { PREFIX_TABLE (PREFIX_0F1C) },
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F1E) },
{ "nopQ", { Ev }, 0 },
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
+ /* REG_0F1C_MOD_0 */
+ {
+ { "cldemote", { Mb }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
/* REG_0F1E_MOD_3 */
{
{ "nopQ", { Ev }, 0 },
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
+ /* PREFIX_0F09 */
+ {
+ { "wbinvd", { XX }, 0 },
+ { "wbnoinvd", { XX }, 0 },
+ },
+
/* PREFIX_0F10 */
{
{ "movups", { XM, EXx }, PREFIX_OPCODE },
{
{ MOD_TABLE (MOD_0F1B_PREFIX_0) },
{ MOD_TABLE (MOD_0F1B_PREFIX_1) },
- { "bndmov", { Ebnd, Gbnd }, 0 },
+ { "bndmov", { EbndS, Gbnd }, 0 },
{ "bndcn", { Gbnd, Ev_bnd }, 0 },
},
+ /* PREFIX_0F1C */
+ {
+ { MOD_TABLE (MOD_0F1C_PREFIX_0) },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F1E */
{
{ "nopQ", { Ev }, PREFIX_OPCODE },
/* PREFIX_0F2C */
{
{ "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
{ "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
{ "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
{ "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
{ "incsspK", { Rdq }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_6 */
+ /* PREFIX_MOD_0_0FAE_REG_6 */
{
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
{ "clwb", { Mb }, PREFIX_OPCODE },
},
+ /* PREFIX_MOD_1_0FAE_REG_6 */
+ {
+ { RM_TABLE (RM_0FAE_REG_6) },
+ { "umonitor", { Eva }, PREFIX_OPCODE },
+ { "tpause", { Edq }, PREFIX_OPCODE },
+ { "umwait", { Edq }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0FAE_REG_7 */
{
{ "clflush", { Mb }, 0 },
{ Bad_Opcode },
},
+ /* PREFIX_0F38F8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ },
+
+ /* PREFIX_0F38F9 */
+ {
+ { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
+ },
+
/* PREFIX_0F3A08 */
{
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38F8) },
+ { PREFIX_TABLE (PREFIX_0F38F9) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* VEX_LEN_0F2C_P_1 */
{
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvttss2si", { Gv, EXdScalar }, 0 },
+ { "vcvttss2si", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2C_P_3 */
{
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2si", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2si", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2D_P_1 */
{
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvtss2si", { Gv, EXdScalar }, 0 },
+ { "vcvtss2si", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2D_P_3 */
{
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2si", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2si", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2E_P_0 */
},
{
/* MOD_0F1A_PREFIX_0 */
- { "bndldx", { Gbnd, Ev_bnd }, 0 },
+ { "bndldx", { Gbnd, Mv_bnd }, 0 },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1B_PREFIX_0 */
- { "bndstx", { Ev_bnd, Gbnd }, 0 },
+ { "bndstx", { Mv_bnd, Gbnd }, 0 },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1B_PREFIX_1 */
- { "bndmk", { Gbnd, Ev_bnd }, 0 },
+ { "bndmk", { Gbnd, Mv_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1C_PREFIX_0 */
+ { REG_TABLE (REG_0F1C_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
},
{
/* MOD_0FAE_REG_6 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
- { RM_TABLE (RM_0FAE_REG_6) },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
+ { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
},
{
/* MOD_0FAE_REG_7 */
/* MOD_0F38F6_PREFIX_0 */
{ "wrssK", { M, Gdq }, PREFIX_OPCODE },
},
+ {
+ /* MOD_0F38F8_PREFIX_2 */
+ { "movdir64b", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F9_PREFIX_0 */
+ { "movdiri", { Em, Gv }, PREFIX_OPCODE },
+ },
{
/* MOD_62_32BIT */
{ "bound{S|}", { Gv, Ma }, 0 },
{ "vmlaunch", { Skip_MODRM }, 0 },
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
+ { "pconfig", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_1 */
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
/* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
VEX.vvvv is 1. */
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- vex.w = 0;
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
need_vex = 0;
need_vex_reg = 0;
vex_w_done = 0;
- vex.evex = 0;
+ memset (&vex, 0, sizeof (vex));
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
{
{ "fmul", { STi, ST }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "fsub!M", { STi, ST }, 0 },
- { "fsubM", { STi, ST }, 0 },
- { "fdiv!M", { STi, ST }, 0 },
- { "fdivM", { STi, ST }, 0 },
+ { "fsub{!M|r}", { STi, ST }, 0 },
+ { "fsub{M|}", { STi, ST }, 0 },
+ { "fdiv{!M|r}", { STi, ST }, 0 },
+ { "fdiv{M|}", { STi, ST }, 0 },
},
/* dd */
{
{ "fmulp", { STi, ST }, 0 },
{ Bad_Opcode },
{ FGRPde_3 },
- { "fsub!Mp", { STi, ST }, 0 },
- { "fsubMp", { STi, ST }, 0 },
- { "fdiv!Mp", { STi, ST }, 0 },
- { "fdivMp", { STi, ST }, 0 },
+ { "fsub{!M|r}p", { STi, ST }, 0 },
+ { "fsub{M|}p", { STi, ST }, 0 },
+ { "fdiv{!M|r}p", { STi, ST }, 0 },
+ { "fdiv{M|}p", { STi, ST }, 0 },
},
/* df */
{
break;
case 'Y':
if (l == 0 && len == 1)
- {
- if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
- break;
- if (rex & REX_W)
- {
- USED_REX (REX_W);
- *obufp++ = 'q';
- }
- break;
- }
+ abort ();
else
{
if (l != 1 || len != 2 || last[0] != 'X')
case q_swap_mode:
oappend ("QWORD PTR ");
break;
+ case dqa_mode:
case m_mode:
if (address_mode == mode_64bit)
oappend ("QWORD PTR ");
oappend ("WORD PTR ");
break;
case v_bnd_mode:
+ case v_bndmk_mode:
default:
break;
}
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == b_swap_mode
+ || bytemode == bnd_swap_mode
|| bytemode == v_swap_mode))
swap_operand ();
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
+ case bnd_swap_mode:
if (reg > 0x3)
{
oappend ("(bad)");
case dqb_mode:
case dqd_mode:
case dqw_mode:
+ case dqa_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
+ names = (address_mode == mode_16bit
+ ? names16 : names);
+ else
+ {
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
+ }
+ break;
case mask_bd_mode:
case mask_mode:
if (reg > 0x7)
case d_scalar_swap_mode:
shift = 2;
break;
- case w_scalar_mode:
+ case w_scalar_mode:
case xmm_mw_mode:
shift = 1;
break;
- case b_scalar_mode:
+ case b_scalar_mode:
case xmm_mb_mode:
shift = 0;
break;
+ case dqa_mode:
+ shift = address_mode == mode_64bit ? 3 : 2;
+ break;
default:
abort ();
}
int havebase;
int haveindex;
int needindex;
+ int needaddr32;
int base, rbase;
int vindex = 0;
int scale = 0;
int addr32flag = !((sizeflag & AFLAG)
|| bytemode == v_bnd_mode
- || bytemode == bnd_mode);
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode);
const char **indexes64 = names64;
const char **indexes32 = names32;
if (address_mode == mode_64bit && !havesib)
riprel = 1;
disp = get32s ();
+ if (riprel && bytemode == v_bndmk_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
}
break;
case 1:
break;
}
- /* In 32bit mode, we need index register to tell [offset] from
- [eiz*1 + offset]. */
- needindex = (havesib
- && !havebase
- && !haveindex
- && address_mode == mode_32bit);
+ needindex = 0;
+ needaddr32 = 0;
+ if (havesib
+ && !havebase
+ && !haveindex
+ && address_mode != mode_16bit)
+ {
+ if (address_mode == mode_64bit)
+ {
+ /* Display eiz instead of addr32. */
+ needindex = addr32flag;
+ needaddr32 = 1;
+ }
+ else
+ {
+ /* In 32-bit mode, we need index register to tell [offset]
+ from [eiz*1 + offset]. */
+ needindex = 1;
+ }
+ }
+
havedisp = (havebase
|| needindex
|| (havesib && (haveindex || scale != 0)));
}
}
- if ((havebase || haveindex || riprel)
+ if ((havebase || haveindex || needaddr32 || riprel)
&& (bytemode != v_bnd_mode)
- && (bytemode != bnd_mode))
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
OP_G (int bytemode, int sizeflag)
{
int add = 0;
+ const char **names;
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
+ {
+ if (address_mode == mode_16bit)
+ names = names16;
+ }
+ else
+ {
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
+ }
+ oappend (names[modrm.reg + add]);
+ break;
case m_mode:
if (address_mode == mode_64bit)
oappend (names64[modrm.reg + add]);
projects / deliverable / binutils-gdb.git / blobdiff