/* Print i386 instructions for GDB, the GNU debugger.
- Copyright (C) 1988-2015 Free Software Foundation, Inc.
+ Copyright (C) 1988-2018 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
the Intel manual for details. */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "opintl.h"
#include "opcode/i386.h"
#include "libiberty.h"
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VEXI4_Fixup (int, int);
static void VZERO_Fixup (int, int);
static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
+static void VPCOM_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
static void BND_Fixup (int, int);
+static void NOTRACK_Fixup (int, int);
static void HLE_Fixup1 (int, int);
static void HLE_Fixup2 (int, int);
static void HLE_Fixup3 (int, int);
static void XMM_Fixup (int, int);
static void CRC32_Fixup (int, int);
static void FXSAVE_Fixup (int, int);
+static void PCMPESTR_Fixup (int, int);
static void OP_LWPCB_E (int, int);
static void OP_LWP_E (int, int);
static void OP_Vex_2src_1 (int, int);
#define Eb { OP_E, b_mode }
#define Ebnd { OP_E, bnd_mode }
#define EbS { OP_E, b_swap_mode }
+#define EbndS { OP_E, bnd_swap_mode }
#define Ev { OP_E, v_mode }
#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
#define Edqw { OP_E, dqw_mode }
-#define EdqwS { OP_E, dqw_swap_mode }
#define Edqb { OP_E, dqb_mode }
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
-#define indirEv { OP_indirE, stack_v_mode }
+#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
#define stackEv { OP_E, stack_v_mode }
#define Em { OP_E, m_mode }
#define EMS { OP_EM, v_swap_mode }
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
+#define EXbScalar { OP_EX, b_scalar_mode }
#define EXw { OP_EX, w_mode }
+#define EXwScalar { OP_EX, w_scalar_mode }
#define EXd { OP_EX, d_mode }
#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
#define Vex128 { OP_VEX, vex128_mode }
#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
-#define VexI4 { VEXI4_Fixup, 0}
#define EXdVex { OP_EX_Vex, d_mode }
#define EXdVexS { OP_EX_Vex, d_swap_mode }
#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
#define VZERO { VZERO_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
+#define VPCOM { VPCOM_Fixup, 0 }
#define EXxEVexR { OP_Rounding, evex_rounding_mode }
#define EXxEVexS { OP_Rounding, evex_sae_mode }
#define Evh3 { HLE_Fixup3, v_mode }
#define BND { BND_Fixup, 0 }
+#define NOTRACK { NOTRACK_Fixup, 0 }
#define cond_jump_flag { NULL, cond_jump_mode }
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
dq_mode,
/* registers like dq_mode, memory like w_mode. */
dqw_mode,
- dqw_swap_mode,
+ /* bounds operand */
bnd_mode,
+ /* bounds operand with operand swapped */
+ bnd_swap_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
+ /* v_mode for indirect branch opcodes. */
+ indir_v_mode,
/* v_mode for stack-related opcodes. */
stack_v_mode,
/* non-quad operand size depends on prefixes */
/* scalar, ignore vector length. */
scalar_mode,
+ /* like b_mode, ignore vector length. */
+ b_scalar_mode,
+ /* like w_mode, ignore vector length. */
+ w_scalar_mode,
/* like d_mode, ignore vector length. */
d_scalar_mode,
/* like d_swap_mode, ignore vector length. */
{
REG_80 = 0,
REG_81,
- REG_82,
+ REG_83,
REG_8F,
REG_C0,
REG_C1,
REG_0F01,
REG_0F0D,
REG_0F18,
+ REG_0F1E_MOD_3,
REG_0F71,
REG_0F72,
REG_0F73,
MOD_0F01_REG_1,
MOD_0F01_REG_2,
MOD_0F01_REG_3,
+ MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
MOD_0F13,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
+ MOD_0F1E_PREFIX_1,
MOD_0F24,
MOD_0F26,
MOD_0F2B_PREFIX_0,
MOD_0FE7_PREFIX_2,
MOD_0FF0_PREFIX_3,
MOD_0F382A_PREFIX_2,
+ MOD_0F38F5_PREFIX_2,
+ MOD_0F38F6_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
MOD_VEX_0F16_PREFIX_0,
MOD_VEX_0F17,
MOD_VEX_0F2B,
+ MOD_VEX_W_0_0F41_P_0_LEN_1,
+ MOD_VEX_W_1_0F41_P_0_LEN_1,
+ MOD_VEX_W_0_0F41_P_2_LEN_1,
+ MOD_VEX_W_1_0F41_P_2_LEN_1,
+ MOD_VEX_W_0_0F42_P_0_LEN_1,
+ MOD_VEX_W_1_0F42_P_0_LEN_1,
+ MOD_VEX_W_0_0F42_P_2_LEN_1,
+ MOD_VEX_W_1_0F42_P_2_LEN_1,
+ MOD_VEX_W_0_0F44_P_0_LEN_1,
+ MOD_VEX_W_1_0F44_P_0_LEN_1,
+ MOD_VEX_W_0_0F44_P_2_LEN_1,
+ MOD_VEX_W_1_0F44_P_2_LEN_1,
+ MOD_VEX_W_0_0F45_P_0_LEN_1,
+ MOD_VEX_W_1_0F45_P_0_LEN_1,
+ MOD_VEX_W_0_0F45_P_2_LEN_1,
+ MOD_VEX_W_1_0F45_P_2_LEN_1,
+ MOD_VEX_W_0_0F46_P_0_LEN_1,
+ MOD_VEX_W_1_0F46_P_0_LEN_1,
+ MOD_VEX_W_0_0F46_P_2_LEN_1,
+ MOD_VEX_W_1_0F46_P_2_LEN_1,
+ MOD_VEX_W_0_0F47_P_0_LEN_1,
+ MOD_VEX_W_1_0F47_P_0_LEN_1,
+ MOD_VEX_W_0_0F47_P_2_LEN_1,
+ MOD_VEX_W_1_0F47_P_2_LEN_1,
+ MOD_VEX_W_0_0F4A_P_0_LEN_1,
+ MOD_VEX_W_1_0F4A_P_0_LEN_1,
+ MOD_VEX_W_0_0F4A_P_2_LEN_1,
+ MOD_VEX_W_1_0F4A_P_2_LEN_1,
+ MOD_VEX_W_0_0F4B_P_0_LEN_1,
+ MOD_VEX_W_1_0F4B_P_0_LEN_1,
+ MOD_VEX_W_0_0F4B_P_2_LEN_1,
MOD_VEX_0F50,
MOD_VEX_0F71_REG_2,
MOD_VEX_0F71_REG_4,
MOD_VEX_0F73_REG_3,
MOD_VEX_0F73_REG_6,
MOD_VEX_0F73_REG_7,
+ MOD_VEX_W_0_0F91_P_0_LEN_0,
+ MOD_VEX_W_1_0F91_P_0_LEN_0,
+ MOD_VEX_W_0_0F91_P_2_LEN_0,
+ MOD_VEX_W_1_0F91_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_0_LEN_0,
+ MOD_VEX_W_0_0F92_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_3_LEN_0,
+ MOD_VEX_W_1_0F92_P_3_LEN_0,
+ MOD_VEX_W_0_0F93_P_0_LEN_0,
+ MOD_VEX_W_0_0F93_P_2_LEN_0,
+ MOD_VEX_W_0_0F93_P_3_LEN_0,
+ MOD_VEX_W_1_0F93_P_3_LEN_0,
+ MOD_VEX_W_0_0F98_P_0_LEN_0,
+ MOD_VEX_W_1_0F98_P_0_LEN_0,
+ MOD_VEX_W_0_0F98_P_2_LEN_0,
+ MOD_VEX_W_1_0F98_P_2_LEN_0,
+ MOD_VEX_W_0_0F99_P_0_LEN_0,
+ MOD_VEX_W_1_0F99_P_0_LEN_0,
+ MOD_VEX_W_0_0F99_P_2_LEN_0,
+ MOD_VEX_W_1_0F99_P_2_LEN_0,
MOD_VEX_0FAE_REG_2,
MOD_VEX_0FAE_REG_3,
MOD_VEX_0FD7_PREFIX_2,
MOD_VEX_0F385A_PREFIX_2,
MOD_VEX_0F388C_PREFIX_2,
MOD_VEX_0F388E_PREFIX_2,
+ MOD_VEX_W_0_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A33_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A33_P_2_LEN_0,
MOD_EVEX_0F10_PREFIX_1,
MOD_EVEX_0F10_PREFIX_3,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
+ RM_0F01_REG_5,
RM_0F01_REG_7,
- RM_0FAE_REG_5,
+ RM_0F1E_MOD_3_REG_7,
RM_0FAE_REG_6,
RM_0FAE_REG_7
};
enum
{
PREFIX_90 = 0,
+ PREFIX_MOD_0_0F01_REG_5,
+ PREFIX_MOD_3_0F01_REG_5_RM_0,
+ PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
PREFIX_0F1A,
PREFIX_0F1B,
+ PREFIX_0F1E,
PREFIX_0F2A,
PREFIX_0F2B,
PREFIX_0F2C,
PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2,
PREFIX_0FAE_REG_3,
+ PREFIX_MOD_0_0FAE_REG_4,
+ PREFIX_MOD_3_0FAE_REG_4,
+ PREFIX_MOD_0_0FAE_REG_5,
+ PREFIX_MOD_3_0FAE_REG_5,
PREFIX_0FAE_REG_6,
PREFIX_0FAE_REG_7,
- PREFIX_RM_0_0FAE_REG_7,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0F38CB,
PREFIX_0F38CC,
PREFIX_0F38CD,
+ PREFIX_0F38CF,
PREFIX_0F38DB,
PREFIX_0F38DC,
PREFIX_0F38DD,
PREFIX_0F38DF,
PREFIX_0F38F0,
PREFIX_0F38F1,
+ PREFIX_0F38F5,
PREFIX_0F38F6,
PREFIX_0F3A08,
PREFIX_0F3A09,
PREFIX_0F3A62,
PREFIX_0F3A63,
PREFIX_0F3ACC,
+ PREFIX_0F3ACE,
+ PREFIX_0F3ACF,
PREFIX_0F3ADF,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
PREFIX_VEX_0F38BD,
PREFIX_VEX_0F38BE,
PREFIX_VEX_0F38BF,
+ PREFIX_VEX_0F38CF,
PREFIX_VEX_0F38DB,
PREFIX_VEX_0F38DC,
PREFIX_VEX_0F38DD,
PREFIX_VEX_0F3A7D,
PREFIX_VEX_0F3A7E,
PREFIX_VEX_0F3A7F,
+ PREFIX_VEX_0F3ACE,
+ PREFIX_VEX_0F3ACF,
PREFIX_VEX_0F3ADF,
PREFIX_VEX_0F3AF0,
PREFIX_EVEX_0F384D,
PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F,
+ PREFIX_EVEX_0F3850,
+ PREFIX_EVEX_0F3851,
+ PREFIX_EVEX_0F3852,
+ PREFIX_EVEX_0F3853,
+ PREFIX_EVEX_0F3854,
+ PREFIX_EVEX_0F3855,
PREFIX_EVEX_0F3858,
PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A,
PREFIX_EVEX_0F385B,
+ PREFIX_EVEX_0F3862,
+ PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865,
PREFIX_EVEX_0F3866,
+ PREFIX_EVEX_0F3870,
+ PREFIX_EVEX_0F3871,
+ PREFIX_EVEX_0F3872,
+ PREFIX_EVEX_0F3873,
PREFIX_EVEX_0F3875,
PREFIX_EVEX_0F3876,
PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B,
PREFIX_EVEX_0F388D,
+ PREFIX_EVEX_0F388F,
PREFIX_EVEX_0F3890,
PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892,
PREFIX_EVEX_0F38CB,
PREFIX_EVEX_0F38CC,
PREFIX_EVEX_0F38CD,
+ PREFIX_EVEX_0F38CF,
+ PREFIX_EVEX_0F38DC,
+ PREFIX_EVEX_0F38DD,
+ PREFIX_EVEX_0F38DE,
+ PREFIX_EVEX_0F38DF,
PREFIX_EVEX_0F3A00,
PREFIX_EVEX_0F3A01,
PREFIX_EVEX_0F3A3F,
PREFIX_EVEX_0F3A42,
PREFIX_EVEX_0F3A43,
+ PREFIX_EVEX_0F3A44,
PREFIX_EVEX_0F3A50,
PREFIX_EVEX_0F3A51,
PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A56,
PREFIX_EVEX_0F3A57,
PREFIX_EVEX_0F3A66,
- PREFIX_EVEX_0F3A67
+ PREFIX_EVEX_0F3A67,
+ PREFIX_EVEX_0F3A70,
+ PREFIX_EVEX_0F3A71,
+ PREFIX_EVEX_0F3A72,
+ PREFIX_EVEX_0F3A73,
+ PREFIX_EVEX_0F3ACE,
+ PREFIX_EVEX_0F3ACF
};
enum
X86_64_63,
X86_64_6D,
X86_64_6F,
+ X86_64_82,
X86_64_9A,
X86_64_C4,
X86_64_C5,
enum
{
THREE_BYTE_0F38 = 0,
- THREE_BYTE_0F3A,
- THREE_BYTE_0F7A
+ THREE_BYTE_0F3A
};
enum
VEX_LEN_0F3841_P_2,
VEX_LEN_0F385A_P_2_M_0,
VEX_LEN_0F38DB_P_2,
- VEX_LEN_0F38DC_P_2,
- VEX_LEN_0F38DD_P_2,
- VEX_LEN_0F38DE_P_2,
- VEX_LEN_0F38DF_P_2,
VEX_LEN_0F38F2_P_0,
VEX_LEN_0F38F3_R_1_P_0,
VEX_LEN_0F38F3_R_2_P_0,
VEX_LEN_0F3A38_P_2,
VEX_LEN_0F3A39_P_2,
VEX_LEN_0F3A41_P_2,
- VEX_LEN_0F3A44_P_2,
VEX_LEN_0F3A46_P_2,
VEX_LEN_0F3A60_P_2,
VEX_LEN_0F3A61_P_2,
VEX_W_0F385A_P_2_M_0,
VEX_W_0F3878_P_2,
VEX_W_0F3879_P_2,
+ VEX_W_0F38CF_P_2,
VEX_W_0F38DB_P_2,
- VEX_W_0F38DC_P_2,
- VEX_W_0F38DD_P_2,
- VEX_W_0F38DE_P_2,
- VEX_W_0F38DF_P_2,
VEX_W_0F3A00_P_2,
VEX_W_0F3A01_P_2,
VEX_W_0F3A02_P_2,
VEX_W_0F3A40_P_2,
VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2,
- VEX_W_0F3A44_P_2,
VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A4B_P_2,
VEX_W_0F3A4C_P_2,
- VEX_W_0F3A60_P_2,
- VEX_W_0F3A61_P_2,
VEX_W_0F3A62_P_2,
VEX_W_0F3A63_P_2,
+ VEX_W_0F3ACE_P_2,
+ VEX_W_0F3ACF_P_2,
VEX_W_0F3ADF_P_2,
EVEX_W_0F10_P_0,
EVEX_W_0F3839_P_1,
EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2,
+ EVEX_W_0F3854_P_2,
+ EVEX_W_0F3855_P_2,
EVEX_W_0F3858_P_2,
EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2,
EVEX_W_0F385B_P_2,
+ EVEX_W_0F3862_P_2,
+ EVEX_W_0F3863_P_2,
EVEX_W_0F3866_P_2,
+ EVEX_W_0F3870_P_2,
+ EVEX_W_0F3871_P_2,
+ EVEX_W_0F3872_P_2,
+ EVEX_W_0F3873_P_2,
EVEX_W_0F3875_P_2,
EVEX_W_0F3878_P_2,
EVEX_W_0F3879_P_2,
EVEX_W_0F3A56_P_2,
EVEX_W_0F3A57_P_2,
EVEX_W_0F3A66_P_2,
- EVEX_W_0F3A67_P_2
+ EVEX_W_0F3A67_P_2,
+ EVEX_W_0F3A70_P_2,
+ EVEX_W_0F3A71_P_2,
+ EVEX_W_0F3A72_P_2,
+ EVEX_W_0F3A73_P_2,
+ EVEX_W_0F3ACE_P_2,
+ EVEX_W_0F3ACF_P_2
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
prefix and behave as 'S' otherwise
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
- 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
- suffix_always is true.
+ 'Y' unused.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
+ '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
+ has no operand size prefix for AMD64 ISA, behave as 'P'
+ otherwise
2 upper case letter macros:
"XY" => print 'x' or 'y' if suffix_always is true or no register
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
- { Bad_Opcode },
- { REG_TABLE (REG_82) },
+ { X86_64_TABLE (X86_64_82) },
+ { REG_TABLE (REG_83) },
{ "testB", { Eb, Gb }, 0 },
{ "testS", { Ev, Gv }, 0 },
{ "xchgB", { Ebh2, Gb }, 0 },
{ "sysret%LP", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
- { "wbinvd", { XX }, 0 },
+ { PREFIX_TABLE (PREFIX_0F09) },
{ Bad_Opcode },
{ "ud2", { XX }, 0 },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_0F1B) },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
+ { PREFIX_TABLE (PREFIX_0F1E) },
{ "nopQ", { Ev }, 0 },
/* 20 */
{ "movZ", { Rm, Cm }, 0 },
/* 78 */
{ PREFIX_TABLE (PREFIX_0F78) },
{ PREFIX_TABLE (PREFIX_0F79) },
- { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
+ { Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_0F7C) },
{ PREFIX_TABLE (PREFIX_0F7D) },
{ "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
/* b8 */
{ PREFIX_TABLE (PREFIX_0FB8) },
- { "ud1", { XX }, 0 },
+ { "ud1S", { Gv, Ev }, 0 },
{ REG_TABLE (REG_0FBA) },
{ "btcS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FBC) },
{ "paddb", { MX, EM }, PREFIX_OPCODE },
{ "paddw", { MX, EM }, PREFIX_OPCODE },
{ "paddd", { MX, EM }, PREFIX_OPCODE },
- { Bad_Opcode },
+ { "ud0S", { Gv, Ev }, 0 },
};
static const unsigned char onebyte_has_modrm[256] = {
/* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
/* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
/* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
- /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
+ /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
/* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
/* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
/* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
- /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
+ /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
/* ------------------------------- */
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
};
{ "xorQ", { Evh1, Iv }, 0 },
{ "cmpQ", { Ev, Iv }, 0 },
},
- /* REG_82 */
+ /* REG_83 */
{
{ "addQ", { Evh1, sIb }, 0 },
{ "orQ", { Evh1, sIb }, 0 },
{ "rcrA", { Eb, Ib }, 0 },
{ "shlA", { Eb, Ib }, 0 },
{ "shrA", { Eb, Ib }, 0 },
- { Bad_Opcode },
+ { "shlA", { Eb, Ib }, 0 },
{ "sarA", { Eb, Ib }, 0 },
},
/* REG_C1 */
{ "rcrQ", { Ev, Ib }, 0 },
{ "shlQ", { Ev, Ib }, 0 },
{ "shrQ", { Ev, Ib }, 0 },
- { Bad_Opcode },
+ { "shlQ", { Ev, Ib }, 0 },
{ "sarQ", { Ev, Ib }, 0 },
},
/* REG_C6 */
{ "rcrA", { Eb, I1 }, 0 },
{ "shlA", { Eb, I1 }, 0 },
{ "shrA", { Eb, I1 }, 0 },
- { Bad_Opcode },
+ { "shlA", { Eb, I1 }, 0 },
{ "sarA", { Eb, I1 }, 0 },
},
/* REG_D1 */
{ "rcrQ", { Ev, I1 }, 0 },
{ "shlQ", { Ev, I1 }, 0 },
{ "shrQ", { Ev, I1 }, 0 },
- { Bad_Opcode },
+ { "shlQ", { Ev, I1 }, 0 },
{ "sarQ", { Ev, I1 }, 0 },
},
/* REG_D2 */
{ "rcrA", { Eb, CL }, 0 },
{ "shlA", { Eb, CL }, 0 },
{ "shrA", { Eb, CL }, 0 },
- { Bad_Opcode },
+ { "shlA", { Eb, CL }, 0 },
{ "sarA", { Eb, CL }, 0 },
},
/* REG_D3 */
{ "rcrQ", { Ev, CL }, 0 },
{ "shlQ", { Ev, CL }, 0 },
{ "shrQ", { Ev, CL }, 0 },
- { Bad_Opcode },
+ { "shlQ", { Ev, CL }, 0 },
{ "sarQ", { Ev, CL }, 0 },
},
/* REG_F6 */
{
{ "testA", { Eb, Ib }, 0 },
- { Bad_Opcode },
+ { "testA", { Eb, Ib }, 0 },
{ "notA", { Ebh1 }, 0 },
{ "negA", { Ebh1 }, 0 },
{ "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
/* REG_F7 */
{
{ "testQ", { Ev, Iv }, 0 },
- { Bad_Opcode },
+ { "testQ", { Ev, Iv }, 0 },
{ "notQ", { Evh1 }, 0 },
{ "negQ", { Evh1 }, 0 },
{ "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
{
{ "incQ", { Evh1 }, 0 },
{ "decQ", { Evh1 }, 0 },
- { "call{T|}", { indirEv, BND }, 0 },
+ { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_3) },
- { "jmp{T|}", { indirEv, BND }, 0 },
+ { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_5) },
{ "pushU", { stackEv }, 0 },
{ Bad_Opcode },
{ MOD_TABLE (MOD_0F01_REG_2) },
{ MOD_TABLE (MOD_0F01_REG_3) },
{ "smswD", { Sv }, 0 },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F01_REG_5) },
{ "lmsw", { Ew }, 0 },
{ MOD_TABLE (MOD_0F01_REG_7) },
},
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
+ /* REG_0F1E_MOD_3 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "rdsspK", { Rdq }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
+ },
/* REG_0F71 */
{
{ Bad_Opcode },
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_MOD_0_0F01_REG_5 */
+ {
+ { Bad_Opcode },
+ { "rstorssp", { Mq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
+ {
+ { Bad_Opcode },
+ { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
+ {
+ { Bad_Opcode },
+ { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F09 */
+ {
+ { "wbinvd", { XX }, 0 },
+ { "wbnoinvd", { XX }, 0 },
+ },
+
/* PREFIX_0F10 */
{
{ "movups", { XM, EXx }, PREFIX_OPCODE },
{
{ MOD_TABLE (MOD_0F1B_PREFIX_0) },
{ MOD_TABLE (MOD_0F1B_PREFIX_1) },
- { "bndmov", { Ebnd, Gbnd }, 0 },
+ { "bndmov", { EbndS, Gbnd }, 0 },
{ "bndcn", { Gbnd, Ev_bnd }, 0 },
},
+ /* PREFIX_0F1E */
+ {
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F1E_PREFIX_1) },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
/* PREFIX_0F2C */
{
{ "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
{ "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
{ "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
{ "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
{ "wrgsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_6 */
+ /* PREFIX_MOD_0_0FAE_REG_4 */
{
- { "xsaveopt", { FXSAVE }, 0 },
- { Bad_Opcode },
- { "clwb", { Mb }, 0 },
+ { "xsave", { FXSAVE }, 0 },
+ { "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_0FAE_REG_7 */
+ /* PREFIX_MOD_3_0FAE_REG_4 */
{
- { "clflush", { Mb }, 0 },
{ Bad_Opcode },
- { "clflushopt", { Mb }, 0 },
+ { "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_RM_0_0FAE_REG_7 */
+ /* PREFIX_MOD_0_0FAE_REG_5 */
{
- { "sfence", { Skip_MODRM }, 0 },
+ { "xrstor", { FXSAVE }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_MOD_3_0FAE_REG_5 */
+ {
+ { "lfence", { Skip_MODRM }, 0 },
+ { "incsspK", { Rdq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0FAE_REG_6 */
+ {
+ { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
+ { "clrssbsy", { Mq }, PREFIX_OPCODE },
+ { "clwb", { Mb }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0FAE_REG_7 */
+ {
+ { "clflush", { Mb }, 0 },
{ Bad_Opcode },
- { "pcommit", { Skip_MODRM }, 0 },
+ { "clflushopt", { Mb }, 0 },
},
/* PREFIX_0FB8 */
/* PREFIX_MOD_3_0FC7_REG_7 */
{
{ "rdseed", { Ev }, 0 },
- { Bad_Opcode },
+ { "rdpid", { Em }, 0 },
{ "rdseed", { Ev }, 0 },
},
{ "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
},
+ /* PREFIX_0F38CF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F38DB */
{
{ Bad_Opcode },
{ "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
},
- /* PREFIX_0F38F6 */
+ /* PREFIX_0F38F5 */
{
{ Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
+ },
+
+ /* PREFIX_0F38F6 */
+ {
+ { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
{ "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
{ "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A62 */
{ "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
},
+ /* PREFIX_0F3ACE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F3ACF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F3ADF */
{
{ Bad_Opcode },
{ "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
+ /* PREFIX_VEX_0F38CF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
+ },
+
/* PREFIX_VEX_0F38DB */
{
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
+ { "vaesenc", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38DD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
+ { "vaesenclast", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38DE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
+ { "vaesdec", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38DF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
+ { "vaesdeclast", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38F2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
+ { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
},
/* PREFIX_VEX_0F3A46 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A5D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A5E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A5F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A6E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A79 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
},
/* PREFIX_VEX_0F3A7E */
{ VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
},
+ /* PREFIX_VEX_0F3ACE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3ACF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
+ },
+
/* PREFIX_VEX_0F3ADF */
{
{ Bad_Opcode },
{ "outs{G|}", { indirDXr, Xz }, 0 },
},
+ /* X86_64_82 */
+ {
+ /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
+ { REG_TABLE (REG_80) },
+ },
+
/* X86_64_9A */
{
{ "Jcall{T|}", { Ap }, 0 },
{ PREFIX_TABLE (PREFIX_0F38CC) },
{ PREFIX_TABLE (PREFIX_0F38CD) },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38F5) },
{ PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_0F3ACC) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3ACE) },
+ { PREFIX_TABLE (PREFIX_0F3ACF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
+};
- /* THREE_BYTE_0F7A */
+static const struct dis386 xop_table[][256] = {
+ /* XOP_08 */
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- { "ptest", { XX }, PREFIX_OPCODE },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
- { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
- { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
- { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
- { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
- /* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phadddq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 50 */
{ Bad_Opcode },
- { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
- { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
- { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
- { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
- /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
- { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 60 */
{ Bad_Opcode },
- { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
- { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
- { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 98 */
+ { Bad_Opcode },
+ { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ /* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ /* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
-};
-
-static const struct dis386 xop_table[][256] = {
- /* XOP_08 */
+ /* XOP_09 */
{
/* 00 */
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { REG_TABLE (REG_XOP_TBM_01) },
+ { REG_TABLE (REG_XOP_TBM_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { REG_TABLE (REG_XOP_LWPCB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
+ { "vfrczss", { XM, EXd }, 0 },
+ { "vfrczsd", { XM, EXq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- /* 90 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ /* 90 */
+ { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
/* 98 */
+ { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
- { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { Bad_Opcode },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
- { Bad_Opcode },
{ Bad_Opcode },
+ { "vphaddbw", { XM, EXxmm }, 0 },
+ { "vphaddbd", { XM, EXxmm }, 0 },
+ { "vphaddbq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vphaddwd", { XM, EXxmm }, 0 },
+ { "vphaddwq", { XM, EXxmm }, 0 },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
- /* d0 */
- { Bad_Opcode },
+ { "vphadddq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* d0 */
{ Bad_Opcode },
+ { "vphaddubw", { XM, EXxmm }, 0 },
+ { "vphaddubd", { XM, EXxmm }, 0 },
+ { "vphaddubq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vphadduwd", { XM, EXxmm }, 0 },
+ { "vphadduwq", { XM, EXxmm }, 0 },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { "vphaddudq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* e0 */
{ Bad_Opcode },
+ { "vphsubbw", { XM, EXxmm }, 0 },
+ { "vphsubwd", { XM, EXxmm }, 0 },
+ { "vphsubdq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* e8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* e8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
- /* XOP_09 */
+ /* XOP_0A */
{
/* 00 */
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_TBM_01) },
- { REG_TABLE (REG_XOP_TBM_02) },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
+ { "bextr", { Gv, Ev, Iq }, 0 },
{ Bad_Opcode },
- { Bad_Opcode },
- { REG_TABLE (REG_XOP_LWPCB) },
+ { REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
- { "vfrczss", { XM, EXd }, 0 },
- { "vfrczsd", { XM, EXq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 90 */
- { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- /* 98 */
- { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* b0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* b8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* c0 */
- { Bad_Opcode },
- { "vphaddbw", { XM, EXxmm }, 0 },
- { "vphaddbd", { XM, EXxmm }, 0 },
- { "vphaddbq", { XM, EXxmm }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { "vphaddwd", { XM, EXxmm }, 0 },
- { "vphaddwq", { XM, EXxmm }, 0 },
- /* c8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "vphadddq", { XM, EXxmm }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* d0 */
- { Bad_Opcode },
- { "vphaddubw", { XM, EXxmm }, 0 },
- { "vphaddubd", { XM, EXxmm }, 0 },
- { "vphaddubq", { XM, EXxmm }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { "vphadduwd", { XM, EXxmm }, 0 },
- { "vphadduwq", { XM, EXxmm }, 0 },
- /* d8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "vphaddudq", { XM, EXxmm }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* e0 */
- { Bad_Opcode },
- { "vphsubbw", { XM, EXxmm }, 0 },
- { "vphsubwd", { XM, EXxmm }, 0 },
- { "vphsubdq", { XM, EXxmm }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* e8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* f0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* f8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- },
- /* XOP_0A */
- {
- /* 00 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 08 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 10 */
- { "bextr", { Gv, Ev, Iq }, 0 },
- { Bad_Opcode },
- { REG_TABLE (REG_XOP_LWP) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 18 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 20 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 28 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 30 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 38 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 40 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 48 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 50 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 58 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 60 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 68 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 70 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 78 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 88 */
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
+ { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
/* VEX_LEN_0F2C_P_1 */
{
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvttss2si", { Gv, EXdScalar }, 0 },
+ { "vcvttss2si", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2C_P_3 */
{
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2si", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2si", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2D_P_1 */
{
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvtss2si", { Gv, EXdScalar }, 0 },
+ { "vcvtss2si", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2D_P_3 */
{
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2si", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2si", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2E_P_0 */
{ VEX_W_TABLE (VEX_W_0F38DB_P_2) },
},
- /* VEX_LEN_0F38DC_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
- },
-
- /* VEX_LEN_0F38DD_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
- },
-
- /* VEX_LEN_0F38DE_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
- },
-
- /* VEX_LEN_0F38DF_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
- },
-
/* VEX_LEN_0F38F2_P_0 */
{
{ "andnS", { Gdq, VexGdq, Edq }, 0 },
{ VEX_W_TABLE (VEX_W_0F3A41_P_2) },
},
- /* VEX_LEN_0F3A44_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
- },
-
/* VEX_LEN_0F3A46_P_2 */
{
{ Bad_Opcode },
/* VEX_LEN_0F3A60_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
+ { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
},
/* VEX_LEN_0F3A61_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
+ { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
},
/* VEX_LEN_0F3A62_P_2 */
/* VEX_LEN_0F3A6A_P_2 */
{
- { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
},
/* VEX_LEN_0F3A6B_P_2 */
{
- { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
},
/* VEX_LEN_0F3A6E_P_2 */
{
- { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
},
/* VEX_LEN_0F3A6F_P_2 */
{
- { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
},
/* VEX_LEN_0F3A7A_P_2 */
{
- { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
},
/* VEX_LEN_0F3A7B_P_2 */
{
- { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
},
/* VEX_LEN_0F3A7E_P_2 */
{
- { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
},
/* VEX_LEN_0F3A7F_P_2 */
{
- { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
},
/* VEX_LEN_0F3ADF_P_2 */
/* VEX_LEN_0FXOP_08_CC */
{
- { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_CD */
{
- { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_CE */
{
- { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_CF */
{
- { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_EC */
{
- { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_ED */
{
- { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_EE */
{
- { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_08_EF */
{
- { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
+ { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
},
/* VEX_LEN_0FXOP_09_80 */
},
{
/* VEX_W_0F41_P_0_LEN_1 */
- { "kandw", { MaskG, MaskVex, MaskR }, 0 },
- { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
},
{
/* VEX_W_0F41_P_2_LEN_1 */
- { "kandb", { MaskG, MaskVex, MaskR }, 0 },
- { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
},
{
/* VEX_W_0F42_P_0_LEN_1 */
- { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
- { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
},
{
/* VEX_W_0F42_P_2_LEN_1 */
- { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
- { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
},
{
/* VEX_W_0F44_P_0_LEN_0 */
- { "knotw", { MaskG, MaskR }, 0 },
- { "knotq", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
},
{
/* VEX_W_0F44_P_2_LEN_0 */
- { "knotb", { MaskG, MaskR }, 0 },
- { "knotd", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
},
{
/* VEX_W_0F45_P_0_LEN_1 */
- { "korw", { MaskG, MaskVex, MaskR }, 0 },
- { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
},
{
/* VEX_W_0F45_P_2_LEN_1 */
- { "korb", { MaskG, MaskVex, MaskR }, 0 },
- { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
},
{
/* VEX_W_0F46_P_0_LEN_1 */
- { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
- { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
},
{
/* VEX_W_0F46_P_2_LEN_1 */
- { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
- { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
},
{
/* VEX_W_0F47_P_0_LEN_1 */
- { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
- { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
},
{
/* VEX_W_0F47_P_2_LEN_1 */
- { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
- { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
},
{
/* VEX_W_0F4A_P_0_LEN_1 */
- { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
- { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
},
{
/* VEX_W_0F4A_P_2_LEN_1 */
- { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
- { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
},
{
/* VEX_W_0F4B_P_0_LEN_1 */
- { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
- { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
},
{
/* VEX_W_0F4B_P_2_LEN_1 */
- { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
},
{
/* VEX_W_0F50_M_0 */
},
{
/* VEX_W_0F91_P_0_LEN_0 */
- { "kmovw", { Ew, MaskG }, 0 },
- { "kmovq", { Eq, MaskG }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
},
{
/* VEX_W_0F91_P_2_LEN_0 */
- { "kmovb", { Eb, MaskG }, 0 },
- { "kmovd", { Ed, MaskG }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
},
{
/* VEX_W_0F92_P_0_LEN_0 */
- { "kmovw", { MaskG, Rdq }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
},
{
/* VEX_W_0F92_P_2_LEN_0 */
- { "kmovb", { MaskG, Rdq }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
},
{
/* VEX_W_0F92_P_3_LEN_0 */
- { "kmovd", { MaskG, Rdq }, 0 },
- { "kmovq", { MaskG, Rdq }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
},
{
/* VEX_W_0F93_P_0_LEN_0 */
- { "kmovw", { Gdq, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
},
{
/* VEX_W_0F93_P_2_LEN_0 */
- { "kmovb", { Gdq, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
},
{
/* VEX_W_0F93_P_3_LEN_0 */
- { "kmovd", { Gdq, MaskR }, 0 },
- { "kmovq", { Gdq, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
},
{
/* VEX_W_0F98_P_0_LEN_0 */
- { "kortestw", { MaskG, MaskR }, 0 },
- { "kortestq", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
},
{
/* VEX_W_0F98_P_2_LEN_0 */
- { "kortestb", { MaskG, MaskR }, 0 },
- { "kortestd", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
},
{
/* VEX_W_0F99_P_0_LEN_0 */
- { "ktestw", { MaskG, MaskR }, 0 },
- { "ktestq", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
},
{
/* VEX_W_0F99_P_2_LEN_0 */
- { "ktestb", { MaskG, MaskR }, 0 },
- { "ktestd", { MaskG, MaskR }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
/* VEX_W_0FAE_R_2_M_0 */
{ "vpbroadcastw", { XM, EXxmm_mw }, 0 },
},
{
- /* VEX_W_0F38DB_P_2 */
- { "vaesimc", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F38DC_P_2 */
- { "vaesenc", { XM, Vex128, EXx }, 0 },
- },
- {
- /* VEX_W_0F38DD_P_2 */
- { "vaesenclast", { XM, Vex128, EXx }, 0 },
- },
- {
- /* VEX_W_0F38DE_P_2 */
- { "vaesdec", { XM, Vex128, EXx }, 0 },
+ /* VEX_W_0F38CF_P_2 */
+ { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F38DF_P_2 */
- { "vaesdeclast", { XM, Vex128, EXx }, 0 },
+ /* VEX_W_0F38DB_P_2 */
+ { "vaesimc", { XM, EXx }, 0 },
},
{
/* VEX_W_0F3A00_P_2 */
},
{
/* VEX_W_0F3A30_P_2_LEN_0 */
- { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
- { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
},
{
/* VEX_W_0F3A31_P_2_LEN_0 */
- { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
- { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
},
{
/* VEX_W_0F3A32_P_2_LEN_0 */
- { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
- { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
},
{
/* VEX_W_0F3A33_P_2_LEN_0 */
- { "kshiftld", { MaskG, MaskR, Ib }, 0 },
- { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
+ { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
},
{
/* VEX_W_0F3A38_P_2 */
/* VEX_W_0F3A42_P_2 */
{ "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3A44_P_2 */
- { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
- },
{
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
/* VEX_W_0F3A4C_P_2 */
{ "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- {
- /* VEX_W_0F3A60_P_2 */
- { "vpcmpestrm", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A61_P_2 */
- { "vpcmpestri", { XM, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3A62_P_2 */
{ "vpcmpistrm", { XM, EXx, Ib }, 0 },
/* VEX_W_0F3A63_P_2 */
{ "vpcmpistri", { XM, EXx, Ib }, 0 },
},
+ {
+ /* VEX_W_0F3ACE_P_2 */
+ { Bad_Opcode },
+ { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3ACF_P_2 */
+ { Bad_Opcode },
+ { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
+ },
{
/* VEX_W_0F3ADF_P_2 */
{ "vaeskeygenassist", { XM, EXx, Ib }, 0 },
{ X86_64_TABLE (X86_64_0F01_REG_3) },
{ RM_TABLE (RM_0F01_REG_3) },
},
+ {
+ /* MOD_0F01_REG_5 */
+ { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
+ { RM_TABLE (RM_0F01_REG_5) },
+ },
{
/* MOD_0F01_REG_7 */
{ "invlpg", { Mb }, 0 },
{ "bndmk", { Gbnd, Ev_bnd }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F1E_PREFIX_1 */
+ { "nopQ", { Ev }, 0 },
+ { REG_TABLE (REG_0F1E_MOD_3) },
+ },
{
/* MOD_0F24 */
{ Bad_Opcode },
},
{
/* MOD_0FAE_REG_4 */
- { "xsave", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
},
{
/* MOD_0FAE_REG_5 */
- { "xrstor", { FXSAVE }, 0 },
- { RM_TABLE (RM_0FAE_REG_5) },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
},
{
/* MOD_0FAE_REG_6 */
/* MOD_0F382A_PREFIX_2 */
{ "movntdqa", { XM, Mx }, 0 },
},
+ {
+ /* MOD_0F38F5_PREFIX_2 */
+ { "wrussK", { M, Gdq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F6_PREFIX_0 */
+ { "wrssK", { M, Gdq }, PREFIX_OPCODE },
+ },
{
/* MOD_62_32BIT */
{ "bound{S|}", { Gv, Ma }, 0 },
/* MOD_VEX_0F2B */
{ VEX_W_TABLE (VEX_W_0F2B_M_0) },
},
+ {
+ /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "korb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ },
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
},
{
- /* MOD_VEX_0F72_REG_6 */
+ /* MOD_VEX_0F72_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_3 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_7 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovw", { Ew, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovq", { Eq, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovb", { Eb, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovd", { Ed, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
+ { "kortestd", { MaskG, MaskR }, 0 },
},
{
- /* MOD_VEX_0F73_REG_2 */
+ /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
+ { "ktestw", { MaskG, MaskR }, 0 },
},
{
- /* MOD_VEX_0F73_REG_3 */
+ /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
+ { "ktestq", { MaskG, MaskR }, 0 },
},
{
- /* MOD_VEX_0F73_REG_6 */
+ /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
+ { "ktestb", { MaskG, MaskR }, 0 },
},
{
- /* MOD_VEX_0F73_REG_7 */
+ /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
+ { "ktestd", { MaskG, MaskR }, 0 },
},
{
/* MOD_VEX_0FAE_REG_2 */
/* MOD_VEX_0F388E_PREFIX_2 */
{ "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
},
+ {
+ /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftld", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
+ },
#define NEED_MOD_TABLE
#include "i386-dis-evex.h"
#undef NEED_MOD_TABLE
{ "vmlaunch", { Skip_MODRM }, 0 },
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
+ { "pconfig", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_1 */
{ "skinit", { Skip_MODRM }, 0 },
{ "invlpga", { Skip_MODRM }, 0 },
},
+ {
+ /* RM_0F01_REG_5 */
+ { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { "wrpkru", { Skip_MODRM }, 0 },
+ },
{
/* RM_0F01_REG_7 */
{ "swapgs", { Skip_MODRM }, 0 },
{ "clzero", { Skip_MODRM }, 0 },
},
{
- /* RM_0FAE_REG_5 */
- { "lfence", { Skip_MODRM }, 0 },
+ /* RM_0F1E_MOD_3_REG_7 */
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
+ { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
/* RM_0FAE_REG_6 */
},
{
/* RM_0FAE_REG_7 */
- { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
+ { "sfence", { Skip_MODRM }, 0 },
+
},
};
#define XACQUIRE_PREFIX (0xf2 | 0x200)
#define XRELEASE_PREFIX (0xf3 | 0x400)
#define BND_PREFIX (0xf2 | 0x400)
+#define NOTRACK_PREFIX (0x3e | 0x100)
static int
ckprefix (void)
return "xrelease";
case BND_PREFIX:
return "bnd";
+ case NOTRACK_PREFIX:
+ return "notrack";
default:
return NULL;
}
rex |= REX_W;
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit
- && vex.register_specifier > 0x7)
+ if (address_mode != mode_64bit)
{
- dp = &bad_opcode;
- return dp;
+ /* In 16/32-bit mode REX_B is silently ignored. */
+ rex &= ~REX_B;
}
vex.length = (*codep & 0x4) ? 256 : 128;
}
codep++;
vex.w = *codep & 0x80;
- if (vex.w && address_mode == mode_64bit)
- rex |= REX_W;
-
- vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit
- && vex.register_specifier > 0x7)
+ if (address_mode == mode_64bit)
{
- dp = &bad_opcode;
- return dp;
+ if (vex.w)
+ rex |= REX_W;
}
-
+ else
+ {
+ /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
+ is ignored, other REX bits are 0 and the highest bit in
+ VEX.vvvv is also ignored (but we mustn't clear it here). */
+ rex = 0;
+ }
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
vindex = *codep++;
dp = &vex_table[vex_table_index][vindex];
end_codep = codep;
- /* There is no MODRM byte for VEX [82|77]. */
- if (vindex != 0x77 && vindex != 0x82)
+ /* There is no MODRM byte for VEX0F 77. */
+ if (vex_table_index != VEX_0F || vindex != 0x77)
{
FETCH_DATA (info, codep + 1);
modrm.mod = (*codep >> 6) & 3;
rex_ignored = rex;
rex = (*codep & 0x80) ? 0 : REX_R;
+ /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
+ VEX.vvvv is 1. */
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit
- && vex.register_specifier > 0x7)
- {
- dp = &bad_opcode;
- return dp;
- }
-
vex.w = 0;
-
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
vindex = *codep++;
dp = &vex_table[dp->op[1].bytemode][vindex];
end_codep = codep;
- /* There is no MODRM byte for VEX [82|77]. */
- if (vindex != 0x77 && vindex != 0x82)
+ /* There is no MODRM byte for VEX 77. */
+ if (vindex != 0x77)
{
FETCH_DATA (info, codep + 1);
modrm.mod = (*codep >> 6) & 3;
rex |= REX_W;
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit)
- {
- /* In 16/32-bit mode silently ignore following bits. */
- rex &= ~REX_B;
- vex.r = 1;
- vex.v = 1;
- vex.register_specifier &= 0x7;
- }
/* The U bit. */
if (!(*codep & 0x4))
vex.mask_register_specifier = *codep & 0x7;
vex.zeroing = *codep & 0x80;
+ if (address_mode != mode_64bit)
+ {
+ /* In 16/32-bit mode silently ignore following bits. */
+ rex &= ~REX_B;
+ vex.r = 1;
+ vex.v = 1;
+ }
+
need_vex = 1;
need_vex_reg = 1;
codep++;
p++;
}
+ if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
+ {
+ (*info->fprintf_func) (info->stream,
+ _("64-bit address is disabled"));
+ return -1;
+ }
+
if (intel_syntax)
{
names64 = intel_names64;
if (*codep == 0x0f)
{
unsigned char threebyte;
- FETCH_DATA (info, codep + 2);
- threebyte = *++codep;
+
+ codep++;
+ FETCH_DATA (info, codep + 1);
+ threebyte = *codep;
dp = &dis386_twobyte[threebyte];
need_modrm = twobyte_has_modrm[*codep];
codep++;
if (op_index[i] != -1 && op_riprel[i])
{
(*info->fprintf_func) (info->stream, " # ");
- (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
+ (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
+ op_address[op_index[i]]), info);
break;
}
"fNsaveIC",
"fNstsw",
/* de */
- "fiadd",
- "fimul",
- "ficom",
- "ficomp",
- "fisub",
- "fisubr",
- "fidiv",
- "fidivr",
+ "fiadd{s|}",
+ "fimul{s|}",
+ "ficom{s|}",
+ "ficomp{s|}",
+ "fisub{s|}",
+ "fisubr{s|}",
+ "fidiv{s|}",
+ "fidivr{s|}",
/* df */
- "fild",
- "fisttp",
- "fist",
- "fistp",
+ "fild{s|}",
+ "fisttp{s|}",
+ "fist{s|}",
+ "fistp{s|}",
"fbld",
"fild{ll|}",
"fbstp",
#define ST { OP_ST, 0 }
#define STi { OP_STi, 0 }
-#define FGRPd9_2 NULL, { { NULL, 0 } }, 0
-#define FGRPd9_4 NULL, { { NULL, 1 } }, 0
-#define FGRPd9_5 NULL, { { NULL, 2 } }, 0
-#define FGRPd9_6 NULL, { { NULL, 3 } }, 0
-#define FGRPd9_7 NULL, { { NULL, 4 } }, 0
-#define FGRPda_5 NULL, { { NULL, 5 } }, 0
-#define FGRPdb_4 NULL, { { NULL, 6 } }, 0
-#define FGRPde_3 NULL, { { NULL, 7 } }, 0
-#define FGRPdf_4 NULL, { { NULL, 8 } }, 0
+#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
+#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
+#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
+#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
+#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
+#define FGRPda_5 NULL, { { NULL, 6 } }, 0
+#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
+#define FGRPde_3 NULL, { { NULL, 8 } }, 0
+#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
static const struct dis386 float_reg[][8] = {
/* d8 */
{ "fmul", { STi, ST }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "fsub!M", { STi, ST }, 0 },
- { "fsubM", { STi, ST }, 0 },
- { "fdiv!M", { STi, ST }, 0 },
- { "fdivM", { STi, ST }, 0 },
+ { "fsub{!M|r}", { STi, ST }, 0 },
+ { "fsub{M|}", { STi, ST }, 0 },
+ { "fdiv{!M|r}", { STi, ST }, 0 },
+ { "fdiv{M|}", { STi, ST }, 0 },
},
/* dd */
{
{ "fmulp", { STi, ST }, 0 },
{ Bad_Opcode },
{ FGRPde_3 },
- { "fsub!Mp", { STi, ST }, 0 },
- { "fsubMp", { STi, ST }, 0 },
- { "fdiv!Mp", { STi, ST }, 0 },
- { "fdivMp", { STi, ST }, 0 },
+ { "fsub{!M|r}p", { STi, ST }, 0 },
+ { "fsub{M|}p", { STi, ST }, 0 },
+ { "fdiv{!M|r}p", { STi, ST }, 0 },
+ { "fdiv{M|}p", { STi, ST }, 0 },
},
/* df */
{
};
static char *fgrps[][8] = {
- /* d9_2 0 */
+ /* Bad opcode 0 */
+ {
+ "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* d9_2 1 */
{
"fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
},
- /* d9_4 1 */
+ /* d9_4 2 */
{
"fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
},
- /* d9_5 2 */
+ /* d9_5 3 */
{
"fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
},
- /* d9_6 3 */
+ /* d9_6 4 */
{
"f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
},
- /* d9_7 4 */
+ /* d9_7 5 */
{
"fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
},
- /* da_5 5 */
+ /* da_5 6 */
{
"(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
},
- /* db_4 6 */
+ /* db_4 7 */
{
"fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
"fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
},
- /* de_3 7 */
+ /* de_3 8 */
{
"(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
},
- /* df_4 8 */
+ /* df_4 9 */
{
"fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
},
cond = 0;
break;
case '{':
- alt = 0;
if (intel_syntax)
{
while (*++p != '|')
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
+ case '&':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && isa64 == intel64)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'T':
if (!intel_syntax
&& address_mode == mode_64bit
break;
case 'Y':
if (l == 0 && len == 1)
- {
- if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
- break;
- if (rex & REX_W)
- {
- USED_REX (REX_W);
- *obufp++ = 'q';
- }
- break;
- }
+ abort ();
else
{
if (l != 1 || len != 2 || last[0] != 'X')
case w_mode:
case dw_mode:
case dqw_mode:
- case dqw_swap_mode:
oappend ("WORD PTR ");
break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ oappend ("QWORD PTR ");
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
oappend ("QWORD PTR ");
break;
}
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
case x_swap_mode:
case evex_x_gscat_mode:
case evex_x_nobcst_mode:
+ case b_scalar_mode:
+ case w_scalar_mode:
if (need_vex)
{
switch (vex.length)
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == b_swap_mode
- || bytemode == v_swap_mode
- || bytemode == dqw_swap_mode))
+ || bytemode == bnd_swap_mode
+ || bytemode == v_swap_mode))
swap_operand ();
switch (bytemode)
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
+ case bnd_swap_mode:
+ if (reg > 0x3)
+ {
+ oappend ("(bad)");
+ return;
+ }
names = names_bnd;
break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ names = names64;
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
break;
}
bytemode = v_mode;
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
case dqd_mode:
case dqw_mode:
- case dqw_swap_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
break;
case mask_bd_mode:
case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
names = names_mask;
break;
case 0:
{
case dqw_mode:
case dw_mode:
- case dqw_swap_mode:
shift = 1;
break;
case dqb_mode:
shift = vex.w ? 3 : 2;
break;
}
- /* Fall through if vex.b == 0. */
+ /* Fall through. */
case xmmqd_mode:
case xmmdw_mode:
case ymmq_mode:
case d_scalar_swap_mode:
shift = 2;
break;
+ case w_scalar_mode:
case xmm_mw_mode:
shift = 1;
break;
+ case b_scalar_mode:
case xmm_mb_mode:
shift = 0;
break;
int scale = 0;
int addr32flag = !((sizeflag & AFLAG)
|| bytemode == v_bnd_mode
- || bytemode == bnd_mode);
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode);
const char **indexes64 = names64;
const char **indexes32 = names32;
if (riprel)
{
set_op (disp, 1);
- oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
+ oappend (!addr32flag ? "(%rip)" : "(%eip)");
}
}
if ((havebase || haveindex || riprel)
&& (bytemode != v_bnd_mode)
- && (bytemode != bnd_mode))
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
if (intel_syntax && riprel)
{
set_op (disp, 1);
- oappend (sizeflag & AFLAG ? "rip" : "eip");
+ oappend (!addr32flag ? "rip" : "eip");
}
*obufp = '\0';
if (havebase)
disp = *codep++;
if ((disp & 0x80) != 0)
disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
break;
case 2:
disp = get16 ();
oappend (names64[modrm.reg + add]);
break;
case bnd_mode:
+ if (modrm.reg > 0x3)
+ {
+ oappend ("(bad)");
+ return;
+ }
oappend (names_bnd[modrm.reg]);
break;
case v_mode:
case dqb_mode:
case dqd_mode:
case dqw_mode:
- case dqw_swap_mode:
USED_REX (REX_W);
if (rex & REX_W)
oappend (names64[modrm.reg + add]);
break;
case mask_bd_mode:
case mask_mode:
+ if ((modrm.reg + add) > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
oappend (names_mask[modrm.reg + add]);
break;
default:
the displacement is added! */
mask = 0xffff;
if ((prefixes & PREFIX_DATA) == 0)
- segment = ((start_pc + codep - start_codep)
+ segment = ((start_pc + (codep - start_codep))
& ~((bfd_vma) 0xffff));
}
if (address_mode != mode_64bit
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == x_swap_mode
|| bytemode == d_swap_mode
- || bytemode == dqw_swap_mode
|| bytemode == d_scalar_swap_mode
|| bytemode == q_swap_mode
|| bytemode == q_scalar_swap_mode))
all_prefixes[last_repnz_prefix] = BND_PREFIX;
}
+/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
+ "notrack". */
+
+static void
+NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (active_seg_prefix == PREFIX_DS
+ && (address_mode != mode_64bit || last_data_prefix < 0))
+ {
+ /* NOTRACK prefix is only valid on indirect branch instructions.
+ NB: DATA prefix is unsupported for Intel64. */
+ active_seg_prefix = 0;
+ all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
+ }
+}
+
/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
"xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
*/
OP_M (bytemode, sizeflag);
}
+static void
+PCMPESTR_Fixup (int bytemode, int sizeflag)
+{
+ /* Add proper suffix to "{,v}pcmpestr{i,m}". */
+ if (!intel_syntax)
+ {
+ char *p = mnemonicendp;
+
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *p++ = 'q';
+ else if (sizeflag & SUFFIX_ALWAYS)
+ *p++ = 'l';
+
+ *p = '\0';
+ mnemonicendp = p;
+ }
+
+ OP_EX (bytemode, sizeflag);
+}
+
/* Display the destination register operand for instructions with
VEX. */
return;
reg = vex.register_specifier;
- if (vex.evex)
- {
- if (!vex.v)
- reg += 16;
- }
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ else if (vex.evex && !vex.v)
+ reg += 16;
if (bytemode == vex_scalar_mode)
{
names = names_xmm;
break;
case dq_mode:
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
break;
case mask_bd_mode:
case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
names = names_mask;
break;
default:
break;
case mask_bd_mode:
case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
names = names_mask;
break;
default:
- abort ();
+ /* See PR binutils/20893 for a reproducer. */
+ oappend ("(bad)");
return;
}
break;
if (base != 5)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 4 byte displacement. */
bytes_before_imm += 4;
if (modrm.rm != 6)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 2 byte displacement. */
bytes_before_imm += 2;
if (rex & REX_B)
reg += 8;
}
- else if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
+ if (address_mode != mode_64bit)
+ reg &= 7;
}
switch (vex.length)
}
if (vex.w)
- oappend (names_xmm[vex.register_specifier]);
+ {
+ unsigned int reg = vex.register_specifier;
+
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names_xmm[reg]);
+ }
else
OP_Vex_2src (bytemode, sizeflag);
}
if (vex.w)
OP_Vex_2src (bytemode, sizeflag);
else
- oappend (names_xmm[vex.register_specifier]);
+ {
+ unsigned int reg = vex.register_specifier;
+
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names_xmm[reg]);
+ }
}
static void
if (!vex_w_done)
{
- vex_w_done = 1;
-
/* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
}
OP_EX_VexReg (bytemode, sizeflag, reg);
-}
-static void
-VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* Skip the immediate byte and check for invalid bits. */
- FETCH_DATA (the_info, codep + 1);
- if (*codep++ & 0xf)
- BadOp ();
+ if (vex_w_done)
+ codep++;
+ vex_w_done = 1;
}
static void
if (bytemode != x_mode)
abort ();
- if (reg & 0xf)
- BadOp ();
-
reg >>= 4;
- if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
+ if (address_mode != mode_64bit)
+ reg &= 7;
switch (vex.length)
{
}
}
+static const struct op xop_cmp_op[] =
+{
+ { STRING_COMMA_LEN ("lt") },
+ { STRING_COMMA_LEN ("le") },
+ { STRING_COMMA_LEN ("gt") },
+ { STRING_COMMA_LEN ("ge") },
+ { STRING_COMMA_LEN ("eq") },
+ { STRING_COMMA_LEN ("neq") },
+ { STRING_COMMA_LEN ("false") },
+ { STRING_COMMA_LEN ("true") }
+};
+
+static void
+VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ unsigned int cmp_type;
+
+ FETCH_DATA (the_info, codep + 1);
+ cmp_type = *codep++ & 0xff;
+ if (cmp_type < ARRAY_SIZE (xop_cmp_op))
+ {
+ char suffix[3];
+ char *p = mnemonicendp - 2;
+
+ /* vpcom* can have both one- and two-lettered suffix. */
+ if (p[0] == 'm')
+ {
+ p++;
+ suffix[0] = p[0];
+ suffix[1] = '\0';
+ }
+ else
+ {
+ suffix[0] = p[0];
+ suffix[1] = p[1];
+ suffix[2] = '\0';
+ }
+
+ sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
+ mnemonicendp += xop_cmp_op[cmp_type].len;
+ }
+ else
+ {
+ /* We have a reserved extension byte. Output it directly. */
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, cmp_type);
+ oappend_maybe_intel (scratchbuf);
+ scratchbuf[0] = '\0';
+ }
+}
+
static const struct op pclmul_op[] =
{
{ STRING_COMMA_LEN ("lql") },
MODRM_CHECK;
codep++;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
const char **names;
+ unsigned int reg = vex.register_specifier;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
- oappend (names[vex.register_specifier]);
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names[reg]);
}
static void
projects / deliverable / binutils-gdb.git / blobdiff