[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 4f128309f7ad83db71fc6ca4167fb17bcab52b02..258a218d87b8f48a34b1ca310a1f8d6b40fd2361 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright (C) 2007-2018 Free Software Foundation, Inc.
+   Copyright (C) 2007-2019 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -43,6 +43,10 @@ enum
   Cpu586,
   /* i686 or better required */
   Cpu686,
+  /* CMOV Instruction support required */
+  CpuCMOV,
+  /* FXSR Instruction support required */
+  CpuFXSR,
   /* CLFLUSH Instruction support required */
   CpuClflush,
   /* NOP Instruction support required */
@@ -174,8 +178,6 @@ enum
   CpuSMAP,
   /* SHA instructions required.  */
   CpuSHA,
-  /* VREX support required  */
-  CpuVREX,
   /* CLFLUSHOPT instruction required */
   CpuClflushOpt,
   /* XSAVES/XRSTORS instruction required */
@@ -204,6 +206,8 @@ enum
   CpuAVX512_VNNI,
   /* Intel AVX-512 BITALG Instructions support required.  */
   CpuAVX512_BITALG,
+  /* Intel AVX-512 BF16 Instructions support required.  */
+  CpuAVX512_BF16,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -264,6 +268,8 @@ typedef union i386_cpu_flags
       unsigned int cpui486:1;
       unsigned int cpui586:1;
       unsigned int cpui686:1;
+      unsigned int cpucmov:1;
+      unsigned int cpufxsr:1;
       unsigned int cpuclflush:1;
       unsigned int cpunop:1;
       unsigned int cpusyscall:1;
@@ -329,7 +335,6 @@ typedef union i386_cpu_flags
       unsigned int cpuprfchw:1;
       unsigned int cpusmap:1;
       unsigned int cpusha:1;
-      unsigned int cpuvrex:1;
       unsigned int cpuclflushopt:1;
       unsigned int cpuxsaves:1;
       unsigned int cpuxsavec:1;
@@ -344,6 +349,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512_vbmi2:1;
       unsigned int cpuavx512_vnni:1;
       unsigned int cpuavx512_bitalg:1;
+      unsigned int cpuavx512_bf16:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
@@ -396,11 +402,12 @@ enum
   /* src/dest swap for floats. */
   FloatR,
   /* needs size prefix if in 32-bit mode */
-  Size16,
+#define SIZE16 1
   /* needs size prefix if in 16-bit mode */
-  Size32,
+#define SIZE32 2
   /* needs size prefix if in 64-bit mode */
-  Size64,
+#define SIZE64 3
+  Size,
   /* check register size.  */
   CheckRegSize,
   /* instruction ignores operand size prefix and in Intel mode ignores
@@ -496,9 +503,11 @@ enum
      0: Set by the REX.W bit.
      1: VEX.W0.  Should always be 0.
      2: VEX.W1.  Should always be 1.
+     3: VEX.WIG. The VEX.W bit is ignored.
    */
 #define VEXW0  1
 #define VEXW1  2
+#define VEXWIG 3
   VexW,
   /* VEX opcode prefix:
      0: VEX 0x0F opcode prefix.
@@ -552,15 +561,26 @@ enum
   EVex,
 
   /* AVX512 masking support:
-       1: Zeroing-masking.
+       1: Zeroing or merging masking depending on operands.
        2: Merging-masking.
        3: Both zeroing and merging masking.
    */
-#define ZEROING_MASKING 1
+#define DYNAMIC_MASKING 1
 #define MERGING_MASKING 2
 #define BOTH_MASKING    3
   Masking,
 
+  /* AVX512 broadcast support.  The number of bytes to broadcast is
+     1 << (Broadcast - 1):
+       1: Byte broadcast.
+       2: Word broadcast.
+       3: Dword broadcast.
+       4: Qword broadcast.
+   */
+#define BYTE_BROADCAST 1
+#define WORD_BROADCAST 2
+#define DWORD_BROADCAST        3
+#define QWORD_BROADCAST        4
   Broadcast,
 
   /* Static rounding control is supported.  */
@@ -569,7 +589,8 @@ enum
   /* Supress All Exceptions is supported.  */
   SAE,
 
-  /* Copressed Disp8*N attribute.  */
+  /* Compressed Disp8*N attribute.  */
+#define DISP8_SHIFT_VL 7
   Disp8MemShift,
 
   /* Default mask isn't allowed.  */
@@ -610,9 +631,7 @@ typedef struct i386_opcode_modifier
   unsigned int jumpintersegment:1;
   unsigned int floatmf:1;
   unsigned int floatr:1;
-  unsigned int size16:1;
-  unsigned int size32:1;
-  unsigned int size64:1;
+  unsigned int size:2;
   unsigned int checkregsize:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
@@ -649,7 +668,7 @@ typedef struct i386_opcode_modifier
   unsigned int noavx:1;
   unsigned int evex:3;
   unsigned int masking:2;
-  unsigned int broadcast:1;
+  unsigned int broadcast:3;
   unsigned int staticrounding:1;
   unsigned int sae:1;
   unsigned int disp8memshift:3;
@@ -736,23 +755,23 @@ enum
   RegMem,
   /* Memory.  */
   Mem,
-  /* BYTE memory. */
+  /* BYTE size. */
   Byte,
-  /* WORD memory. 2 byte */
+  /* WORD size. 2 byte */
   Word,
-  /* DWORD memory. 4 byte */
+  /* DWORD size. 4 byte */
   Dword,
-  /* FWORD memory. 6 byte */
+  /* FWORD size. 6 byte */
   Fword,
-  /* QWORD memory. 8 byte */
+  /* QWORD size. 8 byte */
   Qword,
-  /* TBYTE memory. 10 byte */
+  /* TBYTE size. 10 byte */
   Tbyte,
-  /* XMMWORD memory. */
+  /* XMMWORD size. */
   Xmmword,
-  /* YMMWORD memory. */
+  /* YMMWORD size. */
   Ymmword,
-  /* ZMMWORD memory.  */
+  /* ZMMWORD size.  */
   Zmmword,
   /* Unspecified memory size.  */
   Unspecified,
@@ -810,7 +829,6 @@ typedef union i386_operand_type
       unsigned int jumpabsolute:1;
       unsigned int esseg:1;
       unsigned int regmem:1;
-      unsigned int mem:1;
       unsigned int byte:1;
       unsigned int word:1;
       unsigned int dword:1;
@@ -847,6 +865,8 @@ typedef struct insn_template
                               unset if Regmem --> Reg. */
 #define Opcode_FloatR  0x8 /* Bit to swap src/dest for float insns. */
 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
@@ -887,11 +907,9 @@ typedef struct
 #define RegRex64    0x2  /* Extended 8 bit register.  */
 #define RegVRex            0x4  /* Extended vector register.  */
   unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP  ((unsigned char ) ~0)
 /* EIZ and RIZ are fake index registers.  */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ  (RegIP - 1)
 /* FLAT is a fake segment register (Intel mode).  */
 #define RegFlat     ((unsigned char) ~0)
   signed char dw2_regnum[2];