/* Declarations for Intel 80386 opcode table
- Copyright (C) 2007-2018 Free Software Foundation, Inc.
+ Copyright (C) 2007-2019 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Cpu586,
/* i686 or better required */
Cpu686,
+ /* CMOV Instruction support required */
+ CpuCMOV,
+ /* FXSR Instruction support required */
+ CpuFXSR,
/* CLFLUSH Instruction support required */
CpuClflush,
/* NOP Instruction support required */
CpuAVX512_VNNI,
/* Intel AVX-512 BITALG Instructions support required. */
CpuAVX512_BITALG,
+ /* Intel AVX-512 BF16 Instructions support required. */
+ CpuAVX512_BF16,
+ /* Intel AVX-512 VP2INTERSECT Instructions support required. */
+ CpuAVX512_VP2INTERSECT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
CpuMOVDIRI,
/* MOVDIRR64B instruction required */
CpuMOVDIR64B,
+ /* ENQCMD instruction required */
+ CpuENQCMD,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpui486:1;
unsigned int cpui586:1;
unsigned int cpui686:1;
+ unsigned int cpucmov:1;
+ unsigned int cpufxsr:1;
unsigned int cpuclflush:1;
unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpuavx512_vbmi2:1;
unsigned int cpuavx512_vnni:1;
unsigned int cpuavx512_bitalg:1;
+ unsigned int cpuavx512_bf16:1;
+ unsigned int cpuavx512_vp2intersect:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
unsigned int cpucldemote:1;
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
+ unsigned int cpuenqcmd:1;
+ unsigned int cpurdpru:1;
+ unsigned int cpumcommit:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
{
/* has direction bit. */
D = 0,
- /* set if operands can be words or dwords encoded the canonical way */
+ /* set if operands can be both bytes and words/dwords/qwords, encoded the
+ canonical way; the base_opcode field should hold the encoding for byte
+ operands */
W,
/* load form instruction. Must be placed before store form. */
Load,
/* src/dest swap for floats. */
FloatR,
/* needs size prefix if in 32-bit mode */
- Size16,
+#define SIZE16 1
/* needs size prefix if in 16-bit mode */
- Size32,
+#define SIZE32 2
/* needs size prefix if in 64-bit mode */
- Size64,
+#define SIZE64 3
+ Size,
/* check register size. */
CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
FWait,
/* quick test for string instructions */
IsString,
+ /* RegMem is for instructions with a modrm byte where the register
+ destination operand should be encoded in the mod and regmem fields.
+ Normally, it will be encoded in the reg field. We add a RegMem
+ flag to indicate that it should be encoded in the regmem field. */
+ RegMem,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
/* quick test if NOTRACK prefix is supported */
0: Set by the REX.W bit.
1: VEX.W0. Should always be 0.
2: VEX.W1. Should always be 1.
+ 3: VEX.WIG. The VEX.W bit is ignored.
*/
#define VEXW0 1
#define VEXW1 2
+#define VEXWIG 3
VexW,
/* VEX opcode prefix:
0: VEX 0x0F opcode prefix.
/* Intel64. */
Intel64,
/* The last bitfield in i386_opcode_modifier. */
- Opcode_Modifier_Max
+ Opcode_Modifier_Num
};
typedef struct i386_opcode_modifier
unsigned int jumpintersegment:1;
unsigned int floatmf:1;
unsigned int floatr:1;
- unsigned int size16:1;
- unsigned int size32:1;
- unsigned int size64:1;
+ unsigned int size:2;
unsigned int checkregsize:1;
unsigned int ignoresize:1;
unsigned int defaultsize:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
unsigned int isstring:1;
+ unsigned int regmem:1;
unsigned int bndprefixok:1;
unsigned int notrackprefixok:1;
unsigned int islockable:1;
unsigned int intel64:1;
} i386_opcode_modifier;
+/* Operand classes. */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+ ClassNone,
+ Reg, /* GPRs and FP regs, distinguished by operand size */
+};
+
/* Position of operand_type bits. */
enum
{
- /* Register (qualified by Byte, Word, etc) */
- Reg = 0,
+ /* Class */
+ Class = CLASS_WIDTH - 1,
/* MMX register */
RegMMX,
/* Vector registers */
Debug,
/* Test register */
Test,
- /* 2 bit segment register */
- SReg2,
- /* 3 bit segment register */
- SReg3,
+ /* Segment register */
+ SReg,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
JumpAbsolute,
/* String insn operand with fixed es segment */
EsSeg,
- /* RegMem is for instructions with a modrm byte where the register
- destination operand should be encoded in the mod and regmem fields.
- Normally, it will be encoded in the reg field. We add a RegMem
- flag to the destination register operand to indicate that it should
- be encoded in the regmem field. */
- RegMem,
- /* Memory. */
- Mem,
/* BYTE size. */
Byte,
/* WORD size. 2 byte */
/* Any memory size. */
Anysize,
- /* Vector 4 bit immediate. */
- Vec_Imm4,
-
/* Bound register. */
RegBND,
- /* The number of bitfields in i386_operand_type. */
+ /* The number of bits in i386_operand_type. */
OTNum
};
{
struct
{
- unsigned int reg:1;
+ unsigned int class:CLASS_WIDTH;
unsigned int regmmx:1;
unsigned int regsimd:1;
unsigned int regmask:1;
unsigned int control:1;
unsigned int debug:1;
unsigned int test:1;
- unsigned int sreg2:1;
- unsigned int sreg3:1;
+ unsigned int sreg:1;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
unsigned int shiftcount:1;
unsigned int jumpabsolute:1;
unsigned int esseg:1;
- unsigned int regmem:1;
unsigned int byte:1;
unsigned int word:1;
unsigned int dword:1;
unsigned int zmmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
- unsigned int vec_imm4:1;
unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
/* instruction name sans width suffix ("mov" for movl insns) */
char *name;
- /* how many operands */
- unsigned int operands;
-
/* base_opcode is the fundamental opcode byte without optional
prefix(es). */
unsigned int base_opcode;
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- unsigned int extension_opcode;
+ unsigned short extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
/* Opcode length. */
unsigned char opcode_length;
+ /* how many operands */
+ unsigned char operands;
+
/* cpu feature flags */
i386_cpu_flags cpu_flags;
#define RegRex64 0x2 /* Extended 8 bit register. */
#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP ((unsigned char ) ~0)
/* EIZ and RIZ are fake index registers. */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ (RegIP - 1)
/* FLAT is a fake segment register (Intel mode). */
#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
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