x86: introduce operand type "class"

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 4c38e9eb4bbdd825e4b97bbe74fa758b7ca5f2ed..5c49ac1a528f590acc38203352dd262d04fafefa 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -243,6 +243,10 @@ enum
   CpuMOVDIR64B,
   /* ENQCMD instruction required */
   CpuENQCMD,
+  /* RDPRU instruction required */
+  CpuRDPRU,
+  /* MCOMMIT instruction required */
+  CpuMCOMMIT,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -372,6 +376,8 @@ typedef union i386_cpu_flags
       unsigned int cpumovdiri:1;
       unsigned int cpumovdir64b:1;
       unsigned int cpuenqcmd:1;
+      unsigned int cpurdpru:1;
+      unsigned int cpumcommit:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -387,7 +393,9 @@ enum
 {
   /* has direction bit. */
   D = 0,
-  /* set if operands can be words or dwords encoded the canonical way */
+  /* set if operands can be both bytes and words/dwords/qwords, encoded the
+     canonical way; the base_opcode field should hold the encoding for byte
+     operands  */
   W,
   /* load form instruction. Must be placed before store form.  */
   Load,
@@ -626,7 +634,7 @@ enum
   /* Intel64.  */
   Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
-  Opcode_Modifier_Max
+  Opcode_Modifier_Num
 };
 
 typedef struct i386_opcode_modifier
@@ -694,12 +702,21 @@ typedef struct i386_opcode_modifier
   unsigned int intel64:1;
 } i386_opcode_modifier;
 
+/* Operand classes.  */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+  ClassNone,
+  Reg, /* GPRs and FP regs, distinguished by operand size */
+};
+
 /* Position of operand_type bits.  */
 
 enum
 {
-  /* Register (qualified by Byte, Word, etc) */
-  Reg = 0,
+  /* Class */
+  Class = CLASS_WIDTH - 1,
   /* MMX register */
   RegMMX,
   /* Vector registers */
@@ -757,8 +774,6 @@ enum
   JumpAbsolute,
   /* String insn operand with fixed es segment */
   EsSeg,
-  /* Memory.  */
-  Mem,
   /* BYTE size. */
   Byte,
   /* WORD size. 2 byte */
@@ -785,7 +800,7 @@ enum
   /* Bound register.  */
   RegBND,
 
-  /* The number of bitfields in i386_operand_type.  */
+  /* The number of bits in i386_operand_type.  */
   OTNum
 };
 
@@ -802,7 +817,7 @@ typedef union i386_operand_type
 {
   struct
     {
-      unsigned int reg:1;
+      unsigned int class:CLASS_WIDTH;
       unsigned int regmmx:1;
       unsigned int regsimd:1;
       unsigned int regmask:1;
@@ -852,9 +867,6 @@ typedef struct insn_template
   /* instruction name sans width suffix ("mov" for movl insns) */
   char *name;
 
-  /* how many operands */
-  unsigned int operands;
-
   /* base_opcode is the fundamental opcode byte without optional
      prefix(es).  */
   unsigned int base_opcode;
@@ -871,12 +883,15 @@ typedef struct insn_template
      AMD 3DNow! instructions.
      If this template has no extension opcode (the usual case) use None
      Instructions */
-  unsigned int extension_opcode;
+  unsigned short extension_opcode;
 #define None 0xffff            /* If no extension_opcode is possible.  */
 
   /* Opcode length.  */
   unsigned char opcode_length;
 
+  /* how many operands */
+  unsigned char operands;
+
   /* cpu feature flags */
   i386_cpu_flags cpu_flags;