x86: introduce operand type "class"

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index f89f38b998a2b56fd982b39488ff6b2fd8db6406..5c49ac1a528f590acc38203352dd262d04fafefa 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -243,6 +243,10 @@ enum
   CpuMOVDIR64B,
   /* ENQCMD instruction required */
   CpuENQCMD,
+  /* RDPRU instruction required */
+  CpuRDPRU,
+  /* MCOMMIT instruction required */
+  CpuMCOMMIT,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -372,6 +376,8 @@ typedef union i386_cpu_flags
       unsigned int cpumovdiri:1;
       unsigned int cpumovdir64b:1;
       unsigned int cpuenqcmd:1;
+      unsigned int cpurdpru:1;
+      unsigned int cpumcommit:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -387,7 +393,9 @@ enum
 {
   /* has direction bit. */
   D = 0,
-  /* set if operands can be words or dwords encoded the canonical way */
+  /* set if operands can be both bytes and words/dwords/qwords, encoded the
+     canonical way; the base_opcode field should hold the encoding for byte
+     operands  */
   W,
   /* load form instruction. Must be placed before store form.  */
   Load,
@@ -437,6 +445,11 @@ enum
   FWait,
   /* quick test for string instructions */
   IsString,
+  /* RegMem is for instructions with a modrm byte where the register
+     destination operand should be encoded in the mod and regmem fields.
+     Normally, it will be encoded in the reg field. We add a RegMem
+     flag to indicate that it should be encoded in the regmem field.  */
+  RegMem,
   /* quick test if branch instruction is MPX supported */
   BNDPrefixOk,
   /* quick test if NOTRACK prefix is supported */
@@ -621,7 +634,7 @@ enum
   /* Intel64.  */
   Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
-  Opcode_Modifier_Max
+  Opcode_Modifier_Num
 };
 
 typedef struct i386_opcode_modifier
@@ -649,6 +662,7 @@ typedef struct i386_opcode_modifier
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
+  unsigned int regmem:1;
   unsigned int bndprefixok:1;
   unsigned int notrackprefixok:1;
   unsigned int islockable:1;
@@ -688,12 +702,21 @@ typedef struct i386_opcode_modifier
   unsigned int intel64:1;
 } i386_opcode_modifier;
 
+/* Operand classes.  */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+  ClassNone,
+  Reg, /* GPRs and FP regs, distinguished by operand size */
+};
+
 /* Position of operand_type bits.  */
 
 enum
 {
-  /* Register (qualified by Byte, Word, etc) */
-  Reg = 0,
+  /* Class */
+  Class = CLASS_WIDTH - 1,
   /* MMX register */
   RegMMX,
   /* Vector registers */
@@ -706,10 +729,8 @@ enum
   Debug,
   /* Test register */
   Test,
-  /* 2 bit segment register */
-  SReg2,
-  /* 3 bit segment register */
-  SReg3,
+  /* Segment register */
+  SReg,
   /* 1 bit immediate */
   Imm1,
   /* 8 bit immediate */
@@ -753,14 +774,6 @@ enum
   JumpAbsolute,
   /* String insn operand with fixed es segment */
   EsSeg,
-  /* RegMem is for instructions with a modrm byte where the register
-     destination operand should be encoded in the mod and regmem fields.
-     Normally, it will be encoded in the reg field. We add a RegMem
-     flag to the destination register operand to indicate that it should
-     be encoded in the regmem field.  */
-  RegMem,
-  /* Memory.  */
-  Mem,
   /* BYTE size. */
   Byte,
   /* WORD size. 2 byte */
@@ -784,13 +797,10 @@ enum
   /* Any memory size.  */
   Anysize,
 
-  /* Vector 4 bit immediate.  */
-  Vec_Imm4,
-
   /* Bound register.  */
   RegBND,
 
-  /* The number of bitfields in i386_operand_type.  */
+  /* The number of bits in i386_operand_type.  */
   OTNum
 };
 
@@ -807,15 +817,14 @@ typedef union i386_operand_type
 {
   struct
     {
-      unsigned int reg:1;
+      unsigned int class:CLASS_WIDTH;
       unsigned int regmmx:1;
       unsigned int regsimd:1;
       unsigned int regmask:1;
       unsigned int control:1;
       unsigned int debug:1;
       unsigned int test:1;
-      unsigned int sreg2:1;
-      unsigned int sreg3:1;
+      unsigned int sreg:1;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
@@ -834,7 +843,6 @@ typedef union i386_operand_type
       unsigned int shiftcount:1;
       unsigned int jumpabsolute:1;
       unsigned int esseg:1;
-      unsigned int regmem:1;
       unsigned int byte:1;
       unsigned int word:1;
       unsigned int dword:1;
@@ -846,7 +854,6 @@ typedef union i386_operand_type
       unsigned int zmmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
-      unsigned int vec_imm4:1;
       unsigned int regbnd:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
@@ -860,9 +867,6 @@ typedef struct insn_template
   /* instruction name sans width suffix ("mov" for movl insns) */
   char *name;
 
-  /* how many operands */
-  unsigned int operands;
-
   /* base_opcode is the fundamental opcode byte without optional
      prefix(es).  */
   unsigned int base_opcode;
@@ -879,12 +883,15 @@ typedef struct insn_template
      AMD 3DNow! instructions.
      If this template has no extension opcode (the usual case) use None
      Instructions */
-  unsigned int extension_opcode;
+  unsigned short extension_opcode;
 #define None 0xffff            /* If no extension_opcode is possible.  */
 
   /* Opcode length.  */
   unsigned char opcode_length;
 
+  /* how many operands */
+  unsigned char operands;
+
   /* cpu feature flags */
   i386_cpu_flags cpu_flags;