/* Declarations for Intel 80386 opcode table
- Copyright 2007, 2008, 2009, 2010, 2012
- Free Software Foundation, Inc.
+ Copyright (C) 2007-2018 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
CpuAVX,
/* AVX2 support required */
CpuAVX2,
+ /* Intel AVX-512 Foundation Instructions support required */
+ CpuAVX512F,
+ /* Intel AVX-512 Conflict Detection Instructions support required */
+ CpuAVX512CD,
+ /* Intel AVX-512 Exponential and Reciprocal Instructions support
+ required */
+ CpuAVX512ER,
+ /* Intel AVX-512 Prefetch Instructions support required */
+ CpuAVX512PF,
+ /* Intel AVX-512 VL Instructions support required. */
+ CpuAVX512VL,
+ /* Intel AVX-512 DQ Instructions support required. */
+ CpuAVX512DQ,
+ /* Intel AVX-512 BW Instructions support required. */
+ CpuAVX512BW,
/* Intel L1OM support required */
CpuL1OM,
/* Intel K1OM support required */
CpuK1OM,
+ /* Intel IAMCU support required */
+ CpuIAMCU,
/* Xsave/xrstor New Instructions support required */
CpuXsave,
/* Xsaveopt New Instructions support required */
CpuINVPCID,
/* VMFUNC Instruction required */
CpuVMFUNC,
+ /* Intel MPX Instructions required */
+ CpuMPX,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* RDRSEED instruction required. */
CpuADX,
/* Supports prefetchw and prefetch instructions. */
CpuPRFCHW,
+ /* SMAP instructions required. */
+ CpuSMAP,
+ /* SHA instructions required. */
+ CpuSHA,
+ /* VREX support required */
+ CpuVREX,
+ /* CLFLUSHOPT instruction required */
+ CpuClflushOpt,
+ /* XSAVES/XRSTORS instruction required */
+ CpuXSAVES,
+ /* XSAVEC instruction required */
+ CpuXSAVEC,
+ /* PREFETCHWT1 instruction required */
+ CpuPREFETCHWT1,
+ /* SE1 instruction required */
+ CpuSE1,
+ /* CLWB instruction required */
+ CpuCLWB,
+ /* Intel AVX-512 IFMA Instructions support required. */
+ CpuAVX512IFMA,
+ /* Intel AVX-512 VBMI Instructions support required. */
+ CpuAVX512VBMI,
+ /* Intel AVX-512 4FMAPS Instructions support required. */
+ CpuAVX512_4FMAPS,
+ /* Intel AVX-512 4VNNIW Instructions support required. */
+ CpuAVX512_4VNNIW,
+ /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
+ CpuAVX512_VPOPCNTDQ,
+ /* Intel AVX-512 VBMI2 Instructions support required. */
+ CpuAVX512_VBMI2,
+ /* Intel AVX-512 VNNI Instructions support required. */
+ CpuAVX512_VNNI,
+ /* Intel AVX-512 BITALG Instructions support required. */
+ CpuAVX512_BITALG,
+ /* mwaitx instruction required */
+ CpuMWAITX,
+ /* Clzero instruction required */
+ CpuCLZERO,
+ /* OSPKE instruction required */
+ CpuOSPKE,
+ /* RDPID instruction required */
+ CpuRDPID,
+ /* PTWRITE instruction required */
+ CpuPTWRITE,
+ /* CET instructions support required */
+ CpuIBT,
+ CpuSHSTK,
+ /* GFNI instructions required */
+ CpuGFNI,
+ /* VAES instructions required */
+ CpuVAES,
+ /* VPCLMULQDQ instructions required */
+ CpuVPCLMULQDQ,
+ /* WBNOINVD instructions required */
+ CpuWBNOINVD,
+ /* PCONFIG instructions required */
+ CpuPCONFIG,
+ /* WAITPKG instructions required */
+ CpuWAITPKG,
+ /* CLDEMOTE instruction required */
+ CpuCLDEMOTE,
+ /* MMX register support required */
+ CpuRegMMX,
+ /* XMM register support required */
+ CpuRegXMM,
+ /* YMM register support required */
+ CpuRegYMM,
+ /* ZMM register support required */
+ CpuRegZMM,
+ /* Mask register support required */
+ CpuRegMask,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
unsigned int cpuavx2:1;
+ unsigned int cpuavx512f:1;
+ unsigned int cpuavx512cd:1;
+ unsigned int cpuavx512er:1;
+ unsigned int cpuavx512pf:1;
+ unsigned int cpuavx512vl:1;
+ unsigned int cpuavx512dq:1;
+ unsigned int cpuavx512bw:1;
unsigned int cpul1om:1;
unsigned int cpuk1om:1;
+ unsigned int cpuiamcu:1;
unsigned int cpuxsave:1;
unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpurtm:1;
unsigned int cpuinvpcid:1;
unsigned int cpuvmfunc:1;
+ unsigned int cpumpx:1;
unsigned int cpulm:1;
unsigned int cpurdseed:1;
unsigned int cpuadx:1;
unsigned int cpuprfchw:1;
+ unsigned int cpusmap:1;
+ unsigned int cpusha:1;
+ unsigned int cpuvrex:1;
+ unsigned int cpuclflushopt:1;
+ unsigned int cpuxsaves:1;
+ unsigned int cpuxsavec:1;
+ unsigned int cpuprefetchwt1:1;
+ unsigned int cpuse1:1;
+ unsigned int cpuclwb:1;
+ unsigned int cpuavx512ifma:1;
+ unsigned int cpuavx512vbmi:1;
+ unsigned int cpuavx512_4fmaps:1;
+ unsigned int cpuavx512_4vnniw:1;
+ unsigned int cpuavx512_vpopcntdq:1;
+ unsigned int cpuavx512_vbmi2:1;
+ unsigned int cpuavx512_vnni:1;
+ unsigned int cpuavx512_bitalg:1;
+ unsigned int cpumwaitx:1;
+ unsigned int cpuclzero:1;
+ unsigned int cpuospke:1;
+ unsigned int cpurdpid:1;
+ unsigned int cpuptwrite:1;
+ unsigned int cpuibt:1;
+ unsigned int cpushstk:1;
+ unsigned int cpugfni:1;
+ unsigned int cpuvaes:1;
+ unsigned int cpuvpclmulqdq:1;
+ unsigned int cpuwbnoinvd:1;
+ unsigned int cpupconfig:1;
+ unsigned int cpuwaitpkg:1;
+ unsigned int cpucldemote:1;
+ unsigned int cpuregmmx:1;
+ unsigned int cpuregxmm:1;
+ unsigned int cpuregymm:1;
+ unsigned int cpuregzmm:1;
+ unsigned int cpuregmask:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
D = 0,
/* set if operands can be words or dwords encoded the canonical way */
W,
- /* Skip the current insn and use the next insn in i386-opc.tbl to swap
- operand in encoding. */
- S,
+ /* load form instruction. Must be placed before store form. */
+ Load,
/* insn has a modrm byte. */
Modrm,
/* register is in low 3 bits of opcode */
FloatMF,
/* src/dest swap for floats. */
FloatR,
- /* has float insn direction bit. */
- FloatD,
/* needs size prefix if in 32-bit mode */
Size16,
/* needs size prefix if in 16-bit mode */
FWait,
/* quick test for string instructions */
IsString,
+ /* quick test if branch instruction is MPX supported */
+ BNDPrefixOk,
+ /* quick test if NOTRACK prefix is supported */
+ NoTrackPrefixOk,
/* quick test for lockable instructions */
IsLockable,
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
- /* The first operand must be xmm0 */
- FirstXmm0,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
/* The HLE prefix is OK:
/* deprecated fp insn, gets a warning */
Ugh,
/* insn has VEX prefix:
- 1: 128bit VEX prefix.
+ 1: 128bit VEX prefix (or operand dependent).
2: 256bit VEX prefix.
3: Scalar VEX prefix.
*/
/* Instruction with vector SIB byte:
1: 128bit vector register.
2: 256bit vector register.
+ 3: 512bit vector register.
*/
#define VecSIB128 1
#define VecSIB256 2
+#define VecSIB512 3
VecSIB,
/* SSE to AVX support required */
SSE2AVX,
/* No AVX equivalent */
NoAVX,
- /* Compatible with old (<= 2.8.1) versions of gcc */
- OldGcc,
+
+ /* insn has EVEX prefix:
+ 1: 512bit EVEX prefix.
+ 2: 128bit EVEX prefix.
+ 3: 256bit EVEX prefix.
+ 4: Length-ignored (LIG) EVEX prefix.
+ 5: Length determined from actual operands.
+ */
+#define EVEX512 1
+#define EVEX128 2
+#define EVEX256 3
+#define EVEXLIG 4
+#define EVEXDYN 5
+ EVex,
+
+ /* AVX512 masking support:
+ 1: Zeroing-masking.
+ 2: Merging-masking.
+ 3: Both zeroing and merging masking.
+ */
+#define ZEROING_MASKING 1
+#define MERGING_MASKING 2
+#define BOTH_MASKING 3
+ Masking,
+
+ Broadcast,
+
+ /* Static rounding control is supported. */
+ StaticRounding,
+
+ /* Supress All Exceptions is supported. */
+ SAE,
+
+ /* Copressed Disp8*N attribute. */
+ Disp8MemShift,
+
+ /* Default mask isn't allowed. */
+ NoDefMask,
+
+ /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
+ It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
+ */
+ ImplicitQuadGroup,
+
+ /* Support encoding optimization. */
+ Optimize,
+
/* AT&T mnemonic. */
ATTMnemonic,
/* AT&T syntax. */
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
+ /* AMD64. */
+ AMD64,
+ /* Intel64. */
+ Intel64,
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Max
};
{
unsigned int d:1;
unsigned int w:1;
- unsigned int s:1;
+ unsigned int load:1;
unsigned int modrm:1;
unsigned int shortform:1;
unsigned int jump:1;
unsigned int jumpintersegment:1;
unsigned int floatmf:1;
unsigned int floatr:1;
- unsigned int floatd:1;
unsigned int size16:1;
unsigned int size32:1;
unsigned int size64:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
unsigned int isstring:1;
+ unsigned int bndprefixok:1;
+ unsigned int notrackprefixok:1;
unsigned int islockable:1;
unsigned int regkludge:1;
- unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
unsigned int hleprefixok:2;
unsigned int repprefixok:1;
unsigned int vecsib:2;
unsigned int sse2avx:1;
unsigned int noavx:1;
- unsigned int oldgcc:1;
+ unsigned int evex:3;
+ unsigned int masking:2;
+ unsigned int broadcast:1;
+ unsigned int staticrounding:1;
+ unsigned int sae:1;
+ unsigned int disp8memshift:3;
+ unsigned int nodefmask:1;
+ unsigned int implicitquadgroup:1;
+ unsigned int optimize:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
+ unsigned int amd64:1;
+ unsigned int intel64:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */
enum
{
- /* 8bit register */
- Reg8 = 0,
- /* 16bit register */
- Reg16,
- /* 32bit register */
- Reg32,
- /* 64bit register */
- Reg64,
- /* Floating pointer stack register */
- FloatReg,
+ /* Register (qualified by Byte, Word, etc) */
+ Reg = 0,
/* MMX register */
RegMMX,
- /* SSE register */
- RegXMM,
- /* AVX registers */
- RegYMM,
+ /* Vector registers */
+ RegSIMD,
+ /* Vector Mask registers */
+ RegMask,
/* Control register */
Control,
/* Debug register */
Disp32S,
/* 64 bit displacement */
Disp64,
- /* Accumulator %al/%ax/%eax/%rax */
+ /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
Acc,
- /* Floating pointer top stack register %st(0) */
- FloatAcc,
/* Register which can be used for base or index in memory operand. */
BaseIndex,
/* Register to hold in/out port addr = dx */
Xmmword,
/* YMMWORD memory. */
Ymmword,
+ /* ZMMWORD memory. */
+ Zmmword,
/* Unspecified memory size. */
Unspecified,
/* Any memory size. */
/* Vector 4 bit immediate. */
Vec_Imm4,
+ /* Bound register. */
+ RegBND,
+
/* The last bitfield in i386_operand_type. */
OTMax
};
{
struct
{
- unsigned int reg8:1;
- unsigned int reg16:1;
- unsigned int reg32:1;
- unsigned int reg64:1;
- unsigned int floatreg:1;
+ unsigned int reg:1;
unsigned int regmmx:1;
- unsigned int regxmm:1;
- unsigned int regymm:1;
+ unsigned int regsimd:1;
+ unsigned int regmask:1;
unsigned int control:1;
unsigned int debug:1;
unsigned int test:1;
unsigned int disp32s:1;
unsigned int disp64:1;
unsigned int acc:1;
- unsigned int floatacc:1;
unsigned int baseindex:1;
unsigned int inoutportreg:1;
unsigned int shiftcount:1;
unsigned int tbyte:1;
unsigned int xmmword:1;
unsigned int ymmword:1;
+ unsigned int zmmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
unsigned int vec_imm4:1;
+ unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
unsigned char reg_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
+#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
#define RegRip ((unsigned char ) ~0)
#define RegEip (RegRip - 1)
projects / deliverable / binutils-gdb.git / blobdiff