Enable Intel VPCLMULQDQ instruction.

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 7b0e5b2e5d0e4a6286708e7ee1155d5360d2b216..a14f66d5250c5238ecf46d132e254bda8b4705d3 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright (C) 2007-2014 Free Software Foundation, Inc.
+   Copyright (C) 2007-2017 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -104,12 +104,16 @@ enum
   CpuAVX512PF,
   /* Intel AVX-512 VL Instructions support required.  */
   CpuAVX512VL,
+  /* Intel AVX-512 DQ Instructions support required.  */
+  CpuAVX512DQ,
   /* Intel AVX-512 BW Instructions support required.  */
   CpuAVX512BW,
   /* Intel L1OM support required */
   CpuL1OM,
   /* Intel K1OM support required */
   CpuK1OM,
+  /* Intel IAMCU support required */
+  CpuIAMCU,
   /* Xsave/xrstor New Instructions support required */
   CpuXsave,
   /* Xsaveopt New Instructions support required */
@@ -182,6 +186,48 @@ enum
   CpuPREFETCHWT1,
   /* SE1 instruction required */
   CpuSE1,
+  /* CLWB instruction required */
+  CpuCLWB,
+  /* Intel AVX-512 IFMA Instructions support required.  */
+  CpuAVX512IFMA,
+  /* Intel AVX-512 VBMI Instructions support required.  */
+  CpuAVX512VBMI,
+  /* Intel AVX-512 4FMAPS Instructions support required.  */
+  CpuAVX512_4FMAPS,
+  /* Intel AVX-512 4VNNIW Instructions support required.  */
+  CpuAVX512_4VNNIW,
+  /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
+  CpuAVX512_VPOPCNTDQ,
+  /* Intel AVX-512 VBMI2 Instructions support required.  */
+  CpuAVX512_VBMI2,
+  /* mwaitx instruction required */
+  CpuMWAITX,
+  /* Clzero instruction required */
+  CpuCLZERO,
+  /* OSPKE instruction required */
+  CpuOSPKE,
+  /* RDPID instruction required */
+  CpuRDPID,
+  /* PTWRITE instruction required */
+  CpuPTWRITE,
+  /* CET instruction support required */
+  CpuCET,
+  /* GFNI instructions required */
+  CpuGFNI,
+  /* VAES instructions required */
+  CpuVAES,
+  /* VPCLMULQDQ instructions required */
+  CpuVPCLMULQDQ,
+  /* MMX register support required */
+  CpuRegMMX,
+  /* XMM register support required */
+  CpuRegXMM,
+  /* YMM register support required */
+  CpuRegYMM,
+  /* ZMM register support required */
+  CpuRegZMM,
+  /* Mask register support required */
+  CpuRegMask,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -197,7 +243,7 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-#define CpuUnused      (CpuMax + 1)
+ #define CpuUnused     (CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -241,9 +287,11 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512er:1;
       unsigned int cpuavx512pf:1;
       unsigned int cpuavx512vl:1;
+      unsigned int cpuavx512dq:1;
       unsigned int cpuavx512bw:1;
       unsigned int cpul1om:1;
       unsigned int cpuk1om:1;
+      unsigned int cpuiamcu:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
@@ -280,6 +328,27 @@ typedef union i386_cpu_flags
       unsigned int cpuxsavec:1;
       unsigned int cpuprefetchwt1:1;
       unsigned int cpuse1:1;
+      unsigned int cpuclwb:1;
+      unsigned int cpuavx512ifma:1;
+      unsigned int cpuavx512vbmi:1;
+      unsigned int cpuavx512_4fmaps:1;
+      unsigned int cpuavx512_4vnniw:1;
+      unsigned int cpuavx512_vpopcntdq:1;
+      unsigned int cpuavx512_vbmi2:1;
+      unsigned int cpumwaitx:1;
+      unsigned int cpuclzero:1;
+      unsigned int cpuospke:1;
+      unsigned int cpurdpid:1;
+      unsigned int cpuptwrite:1;
+      unsigned int cpucet:1;
+      unsigned int cpugfni:1;
+      unsigned int cpuvaes:1;
+      unsigned int cpuvpclmulqdq:1;
+      unsigned int cpuregmmx:1;
+      unsigned int cpuregxmm:1;
+      unsigned int cpuregymm:1;
+      unsigned int cpuregzmm:1;
+      unsigned int cpuregmask:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -297,9 +366,8 @@ enum
   D = 0,
   /* set if operands can be words or dwords encoded the canonical way */
   W,
-  /* Skip the current insn and use the next insn in i386-opc.tbl to swap
-     operand in encoding.  */
-  S,
+  /* load form instruction. Must be placed before store form.  */
+  Load,
   /* insn has a modrm byte. */
   Modrm,
   /* register is in low 3 bits of opcode */
@@ -349,6 +417,8 @@ enum
   IsString,
   /* quick test if branch instruction is MPX supported */
   BNDPrefixOk,
+  /* quick test if NOTRACK prefix is supported */
+  NoTrackPrefixOk,
   /* quick test for lockable instructions */
   IsLockable,
   /* fake an extra reg operand for clr, imul and special register
@@ -514,6 +584,11 @@ enum
   /* Default mask isn't allowed.  */
   NoDefMask,
 
+  /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
+     It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
+   */
+  ImplicitQuadGroup,
+
   /* Compatible with old (<= 2.8.1) versions of gcc  */
   OldGcc,
   /* AT&T mnemonic.  */
@@ -522,6 +597,10 @@ enum
   ATTSyntax,
   /* Intel syntax.  */
   IntelSyntax,
+  /* AMD64.  */
+  AMD64,
+  /* Intel64.  */
+  Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
   Opcode_Modifier_Max
 };
@@ -530,7 +609,7 @@ typedef struct i386_opcode_modifier
 {
   unsigned int d:1;
   unsigned int w:1;
-  unsigned int s:1;
+  unsigned int load:1;
   unsigned int modrm:1;
   unsigned int shortform:1;
   unsigned int jump:1;
@@ -555,6 +634,7 @@ typedef struct i386_opcode_modifier
   unsigned int fwait:1;
   unsigned int isstring:1;
   unsigned int bndprefixok:1;
+  unsigned int notrackprefixok:1;
   unsigned int islockable:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
@@ -586,10 +666,13 @@ typedef struct i386_opcode_modifier
   unsigned int sae:1;
   unsigned int disp8memshift:3;
   unsigned int nodefmask:1;
+  unsigned int implicitquadgroup:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
   unsigned int intelsyntax:1;
+  unsigned int amd64:1;
+  unsigned int intel64:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */