/* Declarations for Intel 80386 opcode table
- Copyright (C) 2007-2019 Free Software Foundation, Inc.
+ Copyright (C) 2007-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Load,
/* insn has a modrm byte. */
Modrm,
- /* register is in low 3 bits of opcode */
- ShortForm,
- /* special case for jump insns. */
- Jump,
+ /* special case for jump insns; value has to be 1 */
+#define JUMP 1
/* call and jump */
- JumpDword,
+#define JUMP_DWORD 2
/* loop and jecxz */
- JumpByte,
+#define JUMP_BYTE 3
/* special case for intersegment leaps/calls */
- JumpInterSegment,
+#define JUMP_INTERSEGMENT 4
+ /* absolute address for jump */
+#define JUMP_ABSOLUTE 5
+ Jump,
/* FP insn memory format bit, sized by 0x4 */
FloatMF,
/* src/dest swap for floats. */
IgnoreSize,
/* default insn size depends on mode */
DefaultSize,
+ /* any memory size */
+ Anysize,
/* b suffix on instruction illegal */
No_bSuf,
/* w suffix on instruction illegal */
No_ldSuf,
/* instruction needs FWAIT */
FWait,
- /* quick test for string instructions */
+ /* IsString provides for a quick test for string instructions, and
+ its actual value also indicates which of the operands (if any)
+ requires use of the %es segment. */
+#define IS_STRING_ES_OP0 2
+#define IS_STRING_ES_OP1 3
IsString,
/* RegMem is for instructions with a modrm byte where the register
destination operand should be encoded in the mod and regmem fields.
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
- /* AMD64. */
- AMD64,
- /* Intel64. */
- Intel64,
+ /* ISA64: Don't change the order without other code adjustments.
+ 0: Common to AMD64 and Intel64.
+ 1: AMD64.
+ 2: Intel64.
+ 3: Only in Intel64.
+ */
+#define AMD64 1
+#define INTEL64 2
+#define INTEL64ONLY 3
+ ISA64,
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Num
};
unsigned int w:1;
unsigned int load:1;
unsigned int modrm:1;
- unsigned int shortform:1;
- unsigned int jump:1;
- unsigned int jumpdword:1;
- unsigned int jumpbyte:1;
- unsigned int jumpintersegment:1;
+ unsigned int jump:3;
unsigned int floatmf:1;
unsigned int floatr:1;
unsigned int size:2;
unsigned int checkregsize:1;
unsigned int ignoresize:1;
unsigned int defaultsize:1;
+ unsigned int anysize:1;
unsigned int no_bsuf:1;
unsigned int no_wsuf:1;
unsigned int no_lsuf:1;
unsigned int no_qsuf:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
- unsigned int isstring:1;
+ unsigned int isstring:2;
unsigned int regmem:1;
unsigned int bndprefixok:1;
unsigned int notrackprefixok:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
- unsigned int amd64:1;
- unsigned int intel64:1;
+ unsigned int isa64:2;
} i386_opcode_modifier;
/* Operand classes. */
{
ClassNone,
Reg, /* GPRs and FP regs, distinguished by operand size */
+ SReg, /* Segment register */
+ RegCR, /* Control register */
+ RegDR, /* Debug register */
+ RegTR, /* Test register */
+ RegMMX, /* MMX register */
+ RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
+ RegMask, /* Vector Mask register */
+ RegBND, /* Bound register */
+};
+
+/* Special operand instances. */
+
+#define INSTANCE_WIDTH 3
+enum operand_instance
+{
+ InstanceNone,
+ Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
+ RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
+ RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
+ RegB, /* %bl / %bx / %ebx / %rbx */
};
/* Position of operand_type bits. */
enum
{
- /* Class */
- Class = CLASS_WIDTH - 1,
- /* MMX register */
- RegMMX,
- /* Vector registers */
- RegSIMD,
- /* Vector Mask registers */
- RegMask,
- /* Control register */
- Control,
- /* Debug register */
- Debug,
- /* Test register */
- Test,
- /* Segment register */
- SReg,
+ /* Class and Instance */
+ ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
Disp32S,
/* 64 bit displacement */
Disp64,
- /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
- Acc,
/* Register which can be used for base or index in memory operand. */
BaseIndex,
- /* Register to hold in/out port addr = dx */
- InOutPortReg,
- /* Register to hold shift count = cl */
- ShiftCount,
- /* Absolute address for jump. */
- JumpAbsolute,
- /* String insn operand with fixed es segment */
- EsSeg,
/* BYTE size. */
Byte,
/* WORD size. 2 byte */
Zmmword,
/* Unspecified memory size. */
Unspecified,
- /* Any memory size. */
- Anysize,
-
- /* Bound register. */
- RegBND,
/* The number of bits in i386_operand_type. */
OTNum
struct
{
unsigned int class:CLASS_WIDTH;
- unsigned int regmmx:1;
- unsigned int regsimd:1;
- unsigned int regmask:1;
- unsigned int control:1;
- unsigned int debug:1;
- unsigned int test:1;
- unsigned int sreg:1;
+ unsigned int instance:INSTANCE_WIDTH;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
unsigned int disp32:1;
unsigned int disp32s:1;
unsigned int disp64:1;
- unsigned int acc:1;
unsigned int baseindex:1;
- unsigned int inoutportreg:1;
- unsigned int shiftcount:1;
- unsigned int jumpabsolute:1;
- unsigned int esseg:1;
unsigned int byte:1;
unsigned int word:1;
unsigned int dword:1;
unsigned int ymmword:1;
unsigned int zmmword:1;
unsigned int unspecified:1;
- unsigned int anysize:1;
- unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
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