/* Declarations for Intel 80386 opcode table
- Copyright 2007, 2008, 2009
- Free Software Foundation, Inc.
+ Copyright (C) 2007-2017 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Cpu586,
/* i686 or better required */
Cpu686,
- /* CLFLUSH Instuction support required */
+ /* CLFLUSH Instruction support required */
CpuClflush,
- /* SYSCALL Instuctions support required */
+ /* NOP Instruction support required */
+ CpuNop,
+ /* SYSCALL Instructions support required */
CpuSYSCALL,
/* Floating point support required */
Cpu8087,
CpuSSE4_2,
/* AVX support required */
CpuAVX,
+ /* AVX2 support required */
+ CpuAVX2,
+ /* Intel AVX-512 Foundation Instructions support required */
+ CpuAVX512F,
+ /* Intel AVX-512 Conflict Detection Instructions support required */
+ CpuAVX512CD,
+ /* Intel AVX-512 Exponential and Reciprocal Instructions support
+ required */
+ CpuAVX512ER,
+ /* Intel AVX-512 Prefetch Instructions support required */
+ CpuAVX512PF,
+ /* Intel AVX-512 VL Instructions support required. */
+ CpuAVX512VL,
+ /* Intel AVX-512 DQ Instructions support required. */
+ CpuAVX512DQ,
+ /* Intel AVX-512 BW Instructions support required. */
+ CpuAVX512BW,
/* Intel L1OM support required */
CpuL1OM,
- /* Xsave/xrstor New Instuctions support required */
+ /* Intel K1OM support required */
+ CpuK1OM,
+ /* Intel IAMCU support required */
+ CpuIAMCU,
+ /* Xsave/xrstor New Instructions support required */
CpuXsave,
+ /* Xsaveopt New Instructions support required */
+ CpuXsaveopt,
/* AES support required */
CpuAES,
/* PCLMUL support required */
CpuFMA,
/* FMA4 support required */
CpuFMA4,
- /* MOVBE Instuction support required */
+ /* XOP support required */
+ CpuXOP,
+ /* LWP support required */
+ CpuLWP,
+ /* BMI support required */
+ CpuBMI,
+ /* TBM support required */
+ CpuTBM,
+ /* MOVBE Instruction support required */
CpuMovbe,
+ /* CMPXCHG16B instruction support required. */
+ CpuCX16,
/* EPT Instructions required */
CpuEPT,
- /* RDTSCP Instuction support required */
+ /* RDTSCP Instruction support required */
CpuRdtscp,
+ /* FSGSBASE Instructions required */
+ CpuFSGSBase,
+ /* RDRND Instructions required */
+ CpuRdRnd,
+ /* F16C Instructions required */
+ CpuF16C,
+ /* Intel BMI2 support required */
+ CpuBMI2,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* HLE support required */
+ CpuHLE,
+ /* RTM support required */
+ CpuRTM,
+ /* INVPCID Instructions required */
+ CpuINVPCID,
+ /* VMFUNC Instruction required */
+ CpuVMFUNC,
+ /* Intel MPX Instructions required */
+ CpuMPX,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
+ /* RDRSEED instruction required. */
+ CpuRDSEED,
+ /* Multi-presisionn add-carry instructions are required. */
+ CpuADX,
+ /* Supports prefetchw and prefetch instructions. */
+ CpuPRFCHW,
+ /* SMAP instructions required. */
+ CpuSMAP,
+ /* SHA instructions required. */
+ CpuSHA,
+ /* VREX support required */
+ CpuVREX,
+ /* CLFLUSHOPT instruction required */
+ CpuClflushOpt,
+ /* XSAVES/XRSTORS instruction required */
+ CpuXSAVES,
+ /* XSAVEC instruction required */
+ CpuXSAVEC,
+ /* PREFETCHWT1 instruction required */
+ CpuPREFETCHWT1,
+ /* SE1 instruction required */
+ CpuSE1,
+ /* CLWB instruction required */
+ CpuCLWB,
+ /* Intel AVX-512 IFMA Instructions support required. */
+ CpuAVX512IFMA,
+ /* Intel AVX-512 VBMI Instructions support required. */
+ CpuAVX512VBMI,
+ /* Intel AVX-512 4FMAPS Instructions support required. */
+ CpuAVX512_4FMAPS,
+ /* Intel AVX-512 4VNNIW Instructions support required. */
+ CpuAVX512_4VNNIW,
+ /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
+ CpuAVX512_VPOPCNTDQ,
+ /* mwaitx instruction required */
+ CpuMWAITX,
+ /* Clzero instruction required */
+ CpuCLZERO,
+ /* OSPKE instruction required */
+ CpuOSPKE,
+ /* RDPID instruction required */
+ CpuRDPID,
+ /* PTWRITE instruction required */
+ CpuPTWRITE,
+ /* CET instruction support required */
+ CpuCET,
+ /* MMX register support required */
+ CpuRegMMX,
+ /* XMM register support required */
+ CpuRegXMM,
+ /* YMM register support required */
+ CpuRegYMM,
+ /* ZMM register support required */
+ CpuRegZMM,
+ /* Mask register support required */
+ CpuRegMask,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
/* If you get a compiler error for zero width of the unused field,
comment it out. */
+#if 0
#define CpuUnused (CpuMax + 1)
+#endif
/* We can check if an instruction is available with array instead
of bitfield. */
unsigned int cpui586:1;
unsigned int cpui686:1;
unsigned int cpuclflush:1;
+ unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpu8087:1;
unsigned int cpu287:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
+ unsigned int cpuavx2:1;
+ unsigned int cpuavx512f:1;
+ unsigned int cpuavx512cd:1;
+ unsigned int cpuavx512er:1;
+ unsigned int cpuavx512pf:1;
+ unsigned int cpuavx512vl:1;
+ unsigned int cpuavx512dq:1;
+ unsigned int cpuavx512bw:1;
unsigned int cpul1om:1;
+ unsigned int cpuk1om:1;
+ unsigned int cpuiamcu:1;
unsigned int cpuxsave:1;
+ unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpupclmul:1;
unsigned int cpufma:1;
unsigned int cpufma4:1;
+ unsigned int cpuxop:1;
+ unsigned int cpulwp:1;
+ unsigned int cpubmi:1;
+ unsigned int cputbm:1;
unsigned int cpumovbe:1;
+ unsigned int cpucx16:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
+ unsigned int cpufsgsbase:1;
+ unsigned int cpurdrnd:1;
+ unsigned int cpuf16c:1;
+ unsigned int cpubmi2:1;
+ unsigned int cpulzcnt:1;
+ unsigned int cpuhle:1;
+ unsigned int cpurtm:1;
+ unsigned int cpuinvpcid:1;
+ unsigned int cpuvmfunc:1;
+ unsigned int cpumpx:1;
unsigned int cpulm:1;
+ unsigned int cpurdseed:1;
+ unsigned int cpuadx:1;
+ unsigned int cpuprfchw:1;
+ unsigned int cpusmap:1;
+ unsigned int cpusha:1;
+ unsigned int cpuvrex:1;
+ unsigned int cpuclflushopt:1;
+ unsigned int cpuxsaves:1;
+ unsigned int cpuxsavec:1;
+ unsigned int cpuprefetchwt1:1;
+ unsigned int cpuse1:1;
+ unsigned int cpuclwb:1;
+ unsigned int cpuavx512ifma:1;
+ unsigned int cpuavx512vbmi:1;
+ unsigned int cpuavx512_4fmaps:1;
+ unsigned int cpuavx512_4vnniw:1;
+ unsigned int cpuavx512_vpopcntdq:1;
+ unsigned int cpumwaitx:1;
+ unsigned int cpuclzero:1;
+ unsigned int cpuospke:1;
+ unsigned int cpurdpid:1;
+ unsigned int cpuptwrite:1;
+ unsigned int cpucet:1;
+ unsigned int cpuregmmx:1;
+ unsigned int cpuregxmm:1;
+ unsigned int cpuregymm:1;
+ unsigned int cpuregzmm:1;
+ unsigned int cpuregmask:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
D = 0,
/* set if operands can be words or dwords encoded the canonical way */
W,
- /* Skip the current insn and use the next insn in i386-opc.tbl to swap
- operand in encoding. */
- S,
+ /* load form instruction. Must be placed before store form. */
+ Load,
/* insn has a modrm byte. */
Modrm,
/* register is in low 3 bits of opcode */
Size32,
/* needs size prefix if in 64-bit mode */
Size64,
+ /* check register size. */
+ CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
IgnoreSize,
FWait,
/* quick test for string instructions */
IsString,
+ /* quick test if branch instruction is MPX supported */
+ BNDPrefixOk,
+ /* quick test for lockable instructions */
+ IsLockable,
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
FirstXmm0,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
- /* BYTE is OK in Intel syntax. */
- ByteOkIntel,
+ /* The HLE prefix is OK:
+ 1. With a LOCK prefix.
+ 2. With or without a LOCK prefix.
+ 3. With a RELEASE (0xf3) prefix.
+ */
+#define HLEPrefixNone 0
+#define HLEPrefixLock 1
+#define HLEPrefixAny 2
+#define HLEPrefixRelease 3
+ HLEPrefixOk,
+ /* An instruction on which a "rep" prefix is acceptable. */
+ RepPrefixOk,
/* Convert to DWORD */
ToDword,
/* Convert to QWORD */
/* insn has VEX prefix:
1: 128bit VEX prefix.
2: 256bit VEX prefix.
+ 3: Scalar VEX prefix.
*/
+#define VEX128 1
+#define VEX256 2
+#define VEXScalar 3
Vex,
- /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
- We use VexNDS on insns with VEX DDS since the register-only source
- is the second source register. */
- VexNDS,
- /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
- VexNDD,
- /* insn has VEX W0. */
- VexW0,
- /* insn has VEX W1. */
- VexW1,
- /* insn has VEX 0x0F opcode prefix. */
- Vex0F,
- /* insn has VEX 0x0F38 opcode prefix. */
- Vex0F38,
- /* insn has VEX 0x0F3A opcode prefix. */
- Vex0F3A,
- /* insn has VEX prefix with 3 soures. */
- Vex3Sources,
+ /* How to encode VEX.vvvv:
+ 0: VEX.vvvv must be 1111b.
+ 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
+ the content of source registers will be preserved.
+ VEX.DDS. The second register operand is encoded in VEX.vvvv
+ where the content of first source register will be overwritten
+ by the result.
+ VEX.NDD2. The second destination register operand is encoded in
+ VEX.vvvv for instructions with 2 destination register operands.
+ For assembler, there are no difference between VEX.NDS, VEX.DDS
+ and VEX.NDD2.
+ 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
+ instructions with 1 destination register operand.
+ 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
+ of the operands can access a memory location.
+ */
+#define VEXXDS 1
+#define VEXNDD 2
+#define VEXLWP 3
+ VexVVVV,
+ /* How the VEX.W bit is used:
+ 0: Set by the REX.W bit.
+ 1: VEX.W0. Should always be 0.
+ 2: VEX.W1. Should always be 1.
+ */
+#define VEXW0 1
+#define VEXW1 2
+ VexW,
+ /* VEX opcode prefix:
+ 0: VEX 0x0F opcode prefix.
+ 1: VEX 0x0F38 opcode prefix.
+ 2: VEX 0x0F3A opcode prefix
+ 3: XOP 0x08 opcode prefix.
+ 4: XOP 0x09 opcode prefix
+ 5: XOP 0x0A opcode prefix.
+ */
+#define VEX0F 0
+#define VEX0F38 1
+#define VEX0F3A 2
+#define XOP08 3
+#define XOP09 4
+#define XOP0A 5
+ VexOpcode,
+ /* number of VEX source operands:
+ 0: <= 2 source operands.
+ 1: 2 XOP source operands.
+ 2: 3 source operands.
+ */
+#define XOP2SOURCES 1
+#define VEX3SOURCES 2
+ VexSources,
/* instruction has VEX 8 bit imm */
VexImmExt,
+ /* Instruction with vector SIB byte:
+ 1: 128bit vector register.
+ 2: 256bit vector register.
+ 3: 512bit vector register.
+ */
+#define VecSIB128 1
+#define VecSIB256 2
+#define VecSIB512 3
+ VecSIB,
/* SSE to AVX support required */
SSE2AVX,
/* No AVX equivalent */
NoAVX,
+
+ /* insn has EVEX prefix:
+ 1: 512bit EVEX prefix.
+ 2: 128bit EVEX prefix.
+ 3: 256bit EVEX prefix.
+ 4: Length-ignored (LIG) EVEX prefix.
+ */
+#define EVEX512 1
+#define EVEX128 2
+#define EVEX256 3
+#define EVEXLIG 4
+ EVex,
+
+ /* AVX512 masking support:
+ 1: Zeroing-masking.
+ 2: Merging-masking.
+ 3: Both zeroing and merging masking.
+ */
+#define ZEROING_MASKING 1
+#define MERGING_MASKING 2
+#define BOTH_MASKING 3
+ Masking,
+
+ /* Input element size of vector insn:
+ 0: 32bit.
+ 1: 64bit.
+ */
+ VecESize,
+
+ /* Broadcast factor.
+ 0: No broadcast.
+ 1: 1to16 broadcast.
+ 2: 1to8 broadcast.
+ */
+#define NO_BROADCAST 0
+#define BROADCAST_1TO16 1
+#define BROADCAST_1TO8 2
+#define BROADCAST_1TO4 3
+#define BROADCAST_1TO2 4
+ Broadcast,
+
+ /* Static rounding control is supported. */
+ StaticRounding,
+
+ /* Supress All Exceptions is supported. */
+ SAE,
+
+ /* Copressed Disp8*N attribute. */
+ Disp8MemShift,
+
+ /* Default mask isn't allowed. */
+ NoDefMask,
+
+ /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
+ It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
+ */
+ ImplicitQuadGroup,
+
/* Compatible with old (<= 2.8.1) versions of gcc */
OldGcc,
/* AT&T mnemonic. */
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
+ /* AMD64. */
+ AMD64,
+ /* Intel64. */
+ Intel64,
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Max
};
{
unsigned int d:1;
unsigned int w:1;
- unsigned int s:1;
+ unsigned int load:1;
unsigned int modrm:1;
unsigned int shortform:1;
unsigned int jump:1;
unsigned int size16:1;
unsigned int size32:1;
unsigned int size64:1;
+ unsigned int checkregsize:1;
unsigned int ignoresize:1;
unsigned int defaultsize:1;
unsigned int no_bsuf:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
unsigned int isstring:1;
+ unsigned int bndprefixok:1;
+ unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
- unsigned int byteokintel:1;
+ unsigned int hleprefixok:2;
+ unsigned int repprefixok:1;
unsigned int todword:1;
unsigned int toqword:1;
unsigned int addrprefixop0:1;
unsigned int rex64:1;
unsigned int ugh:1;
unsigned int vex:2;
- unsigned int vexnds:1;
- unsigned int vexndd:1;
- unsigned int vexw0:1;
- unsigned int vexw1:1;
- unsigned int vex0f:1;
- unsigned int vex0f38:1;
- unsigned int vex0f3a:1;
- unsigned int vex3sources:1;
+ unsigned int vexvvvv:2;
+ unsigned int vexw:2;
+ unsigned int vexopcode:3;
+ unsigned int vexsources:2;
unsigned int veximmext:1;
+ unsigned int vecsib:2;
unsigned int sse2avx:1;
unsigned int noavx:1;
+ unsigned int evex:3;
+ unsigned int masking:2;
+ unsigned int vecesize:1;
+ unsigned int broadcast:3;
+ unsigned int staticrounding:1;
+ unsigned int sae:1;
+ unsigned int disp8memshift:3;
+ unsigned int nodefmask:1;
+ unsigned int implicitquadgroup:1;
unsigned int oldgcc:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
+ unsigned int amd64:1;
+ unsigned int intel64:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */
RegXMM,
/* AVX registers */
RegYMM,
+ /* AVX512 registers */
+ RegZMM,
+ /* Vector Mask registers */
+ RegMask,
/* Control register */
Control,
/* Debug register */
Xmmword,
/* YMMWORD memory. */
Ymmword,
+ /* ZMMWORD memory. */
+ Zmmword,
/* Unspecified memory size. */
Unspecified,
/* Any memory size. */
Anysize,
+ /* Vector 4 bit immediate. */
+ Vec_Imm4,
+
+ /* Bound register. */
+ RegBND,
+
+ /* Vector 8bit displacement */
+ Vec_Disp8,
+
/* The last bitfield in i386_operand_type. */
OTMax
};
unsigned int regmmx:1;
unsigned int regxmm:1;
unsigned int regymm:1;
+ unsigned int regzmm:1;
+ unsigned int regmask:1;
unsigned int control:1;
unsigned int debug:1;
unsigned int test:1;
unsigned int tbyte:1;
unsigned int xmmword:1;
unsigned int ymmword:1;
+ unsigned int zmmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
+ unsigned int vec_imm4:1;
+ unsigned int regbnd:1;
+ unsigned int vec_disp8:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
- If this template has no extension opcode (the usual case) use None
+ If this template has no extension opcode (the usual case) use None
Instructions */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
unsigned char reg_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
+#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
#define RegRip ((unsigned char ) ~0)
#define RegEip (RegRip - 1)
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