X86: Add pseudo prefixes to control encoding

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index a8f63330a7750850a334470f63323e61325a44db..d1a6a4505824a10d53c4a55b0b38109be36d2491 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright (C) 2007-2014 Free Software Foundation, Inc.
+   Copyright (C) 2007-2017 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -112,6 +112,8 @@ enum
   CpuL1OM,
   /* Intel K1OM support required */
   CpuK1OM,
+  /* Intel IAMCU support required */
+  CpuIAMCU,
   /* Xsave/xrstor New Instructions support required */
   CpuXsave,
   /* Xsaveopt New Instructions support required */
@@ -186,12 +188,38 @@ enum
   CpuSE1,
   /* CLWB instruction required */
   CpuCLWB,
-  /* PCOMMIT instruction required */
-  CpuPCOMMIT,
   /* Intel AVX-512 IFMA Instructions support required.  */
   CpuAVX512IFMA,
   /* Intel AVX-512 VBMI Instructions support required.  */
   CpuAVX512VBMI,
+  /* Intel AVX-512 4FMAPS Instructions support required.  */
+  CpuAVX512_4FMAPS,
+  /* Intel AVX-512 4VNNIW Instructions support required.  */
+  CpuAVX512_4VNNIW,
+  /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
+  CpuAVX512_VPOPCNTDQ,
+  /* mwaitx instruction required */
+  CpuMWAITX,
+  /* Clzero instruction required */
+  CpuCLZERO,
+  /* OSPKE instruction required */
+  CpuOSPKE,
+  /* RDPID instruction required */
+  CpuRDPID,
+  /* PTWRITE instruction required */
+  CpuPTWRITE,
+  /* CET instruction support required */
+  CpuCET,
+  /* MMX register support required */
+  CpuRegMMX,
+  /* XMM register support required */
+  CpuRegXMM,
+  /* YMM register support required */
+  CpuRegYMM,
+  /* ZMM register support required */
+  CpuRegZMM,
+  /* Mask register support required */
+  CpuRegMask,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -207,7 +235,9 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
+#if 0
 #define CpuUnused      (CpuMax + 1)
+#endif
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -255,6 +285,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512bw:1;
       unsigned int cpul1om:1;
       unsigned int cpuk1om:1;
+      unsigned int cpuiamcu:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
@@ -292,9 +323,22 @@ typedef union i386_cpu_flags
       unsigned int cpuprefetchwt1:1;
       unsigned int cpuse1:1;
       unsigned int cpuclwb:1;
-      unsigned int cpupcommit:1;
       unsigned int cpuavx512ifma:1;
       unsigned int cpuavx512vbmi:1;
+      unsigned int cpuavx512_4fmaps:1;
+      unsigned int cpuavx512_4vnniw:1;
+      unsigned int cpuavx512_vpopcntdq:1;
+      unsigned int cpumwaitx:1;
+      unsigned int cpuclzero:1;
+      unsigned int cpuospke:1;
+      unsigned int cpurdpid:1;
+      unsigned int cpuptwrite:1;
+      unsigned int cpucet:1;
+      unsigned int cpuregmmx:1;
+      unsigned int cpuregxmm:1;
+      unsigned int cpuregymm:1;
+      unsigned int cpuregzmm:1;
+      unsigned int cpuregmask:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -312,9 +356,8 @@ enum
   D = 0,
   /* set if operands can be words or dwords encoded the canonical way */
   W,
-  /* Skip the current insn and use the next insn in i386-opc.tbl to swap
-     operand in encoding.  */
-  S,
+  /* load form instruction. Must be placed before store form.  */
+  Load,
   /* insn has a modrm byte. */
   Modrm,
   /* register is in low 3 bits of opcode */
@@ -529,6 +572,11 @@ enum
   /* Default mask isn't allowed.  */
   NoDefMask,
 
+  /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
+     It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
+   */
+  ImplicitQuadGroup,
+
   /* Compatible with old (<= 2.8.1) versions of gcc  */
   OldGcc,
   /* AT&T mnemonic.  */
@@ -537,6 +585,10 @@ enum
   ATTSyntax,
   /* Intel syntax.  */
   IntelSyntax,
+  /* AMD64.  */
+  AMD64,
+  /* Intel64.  */
+  Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
   Opcode_Modifier_Max
 };
@@ -545,7 +597,7 @@ typedef struct i386_opcode_modifier
 {
   unsigned int d:1;
   unsigned int w:1;
-  unsigned int s:1;
+  unsigned int load:1;
   unsigned int modrm:1;
   unsigned int shortform:1;
   unsigned int jump:1;
@@ -601,10 +653,13 @@ typedef struct i386_opcode_modifier
   unsigned int sae:1;
   unsigned int disp8memshift:3;
   unsigned int nodefmask:1;
+  unsigned int implicitquadgroup:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
   unsigned int intelsyntax:1;
+  unsigned int amd64:1;
+  unsigned int intel64:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */