CpuMOVDIR64B,
/* ENQCMD instruction required */
CpuENQCMD,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
unsigned int cpuenqcmd:1;
+ unsigned int cpurdpru:1;
+ unsigned int cpumcommit:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
{
/* has direction bit. */
D = 0,
- /* set if operands can be words or dwords encoded the canonical way */
+ /* set if operands can be both bytes and words/dwords/qwords, encoded the
+ canonical way; the base_opcode field should hold the encoding for byte
+ operands */
W,
/* load form instruction. Must be placed before store form. */
Load,
unsigned int intel64:1;
} i386_opcode_modifier;
+/* Operand classes. */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+ ClassNone,
+ Reg, /* GPRs and FP regs, distinguished by operand size */
+ SReg, /* Segment register */
+};
+
/* Position of operand_type bits. */
enum
{
- /* Register (qualified by Byte, Word, etc) */
- Reg = 0,
+ /* Class */
+ Class = CLASS_WIDTH - 1,
/* MMX register */
RegMMX,
/* Vector registers */
Debug,
/* Test register */
Test,
- /* Segment register */
- SReg,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
/* Bound register. */
RegBND,
- /* The number of bitfields in i386_operand_type. */
+ /* The number of bits in i386_operand_type. */
OTNum
};
{
struct
{
- unsigned int reg:1;
+ unsigned int class:CLASS_WIDTH;
unsigned int regmmx:1;
unsigned int regsimd:1;
unsigned int regmask:1;
unsigned int control:1;
unsigned int debug:1;
unsigned int test:1;
- unsigned int sreg:1;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
/* instruction name sans width suffix ("mov" for movl insns) */
char *name;
- /* how many operands */
- unsigned int operands;
-
/* base_opcode is the fundamental opcode byte without optional
prefix(es). */
unsigned int base_opcode;
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- unsigned int extension_opcode;
+ unsigned short extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
/* Opcode length. */
unsigned char opcode_length;
+ /* how many operands */
+ unsigned char operands;
+
/* cpu feature flags */
i386_cpu_flags cpu_flags;