CpuSSSE3,
/* SSE4a support required */
CpuSSE4a,
- /* ABM New Instructions required */
- CpuABM,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* POPCNT support required */
+ CpuPOPCNT,
/* SSE4.1 support required */
CpuSSE4_1,
/* SSE4.2 support required */
CpuF16C,
/* Intel BMI2 support required */
CpuBMI2,
- /* LZCNT support required */
- CpuLZCNT,
/* HLE support required */
CpuHLE,
/* RTM support required */
unsigned int cpusmx:1;
unsigned int cpussse3:1;
unsigned int cpusse4a:1;
- unsigned int cpuabm:1;
+ unsigned int cpulzcnt:1;
+ unsigned int cpupopcnt:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
unsigned int cpurdrnd:1;
unsigned int cpuf16c:1;
unsigned int cpubmi2:1;
- unsigned int cpulzcnt:1;
unsigned int cpuhle:1;
unsigned int cpurtm:1;
unsigned int cpuinvpcid:1;
Load,
/* insn has a modrm byte. */
Modrm,
- /* register is in low 3 bits of opcode */
- ShortForm,
/* special case for jump insns; value has to be 1 */
#define JUMP 1
/* call and jump */
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
- /* AMD64. */
- AMD64,
- /* Intel64. */
- Intel64,
+ /* ISA64: Don't change the order without other code adjustments.
+ 0: Common to AMD64 and Intel64.
+ 1: AMD64.
+ 2: Intel64.
+ 3: Only in Intel64.
+ */
+#define AMD64 1
+#define INTEL64 2
+#define INTEL64ONLY 3
+ ISA64,
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Num
};
unsigned int w:1;
unsigned int load:1;
unsigned int modrm:1;
- unsigned int shortform:1;
unsigned int jump:3;
unsigned int floatmf:1;
unsigned int floatr:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
- unsigned int amd64:1;
- unsigned int intel64:1;
+ unsigned int isa64:2;
} i386_opcode_modifier;
/* Operand classes. */