// i386 register table.
-// Copyright (C) 2007-2017 Free Software Foundation, Inc.
+// Copyright (C) 2007-2019 Free Software Foundation, Inc.
//
// This file is part of the GNU opcodes library.
//
// 02110-1301, USA.
// Make %st first as we test for it.
-st, FloatReg|FloatAcc, 0, 0, 11, 33
+st, FloatReg|Acc, 0, 0, 11, 33
// 8 bit regs
-al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
+al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval
cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
// 16 bit regs
-ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
+ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval
cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
// 32 bit regs
-eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
+eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval
ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
-rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
+rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0
rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
mm5, RegMMX, 0, 5, 34, 46
mm6, RegMMX, 0, 6, 35, 47
mm7, RegMMX, 0, 7, 36, 48
-xmm0, RegXMM, 0, 0, 21, 17
+xmm0, RegXMM|Acc, 0, 0, 21, 17
xmm1, RegXMM, 0, 1, 22, 18
xmm2, RegXMM, 0, 2, 23, 19
xmm3, RegXMM, 0, 3, 24, 20
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
-// No type will make these registers rejected for all purposes except
+// No Reg will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
-rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
-eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
-// No type will make these registers rejected for all purposes except
+rip, Qword, RegRex64, RegIP, Dw2Inval, 16
+eip, Dword, RegRex64, RegIP, 8, Dw2Inval
+// No Reg will make these registers rejected for all purposes except
// for addressing.
-riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
-eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
+riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
+eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
// fp regs.
-st(0), FloatReg|FloatAcc, 0, 0, 11, 33
+st(0), FloatReg|Acc, 0, 0, 11, 33
st(1), FloatReg, 0, 1, 12, 34
st(2), FloatReg, 0, 2, 13, 35
st(3), FloatReg, 0, 3, 14, 36