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[deliverable/binutils-gdb.git] / opcodes / m32r-desc.h

diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 6a3636cd55c82642a2c1549d9b9e5a346d42d2f7..e6cf95417b6c35f34af1df3311b12a0cef284bc9 100644 (file)
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -28,29 +28,37 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_ARCH m32r
 
 /* Given symbol S, return m32r_cgen_<S>.  */
-#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) m32r##_cgen_##s
+#else
+#define CGEN_SYM(s) m32r/**/_cgen_/**/s
+#endif
+
 
 /* Selected cpu families.  */
 #define HAVE_CPU_M32RBF
+#define HAVE_CPU_M32RXF
 
 #define CGEN_INSN_LSB0_P 0
 
+/* Minimum size of any insn (in bytes).  */
+#define CGEN_MIN_INSN_SIZE 2
+
 /* Maximum size of any insn (in bytes).  */
 #define CGEN_MAX_INSN_SIZE 4
 
 #define CGEN_INT_INSN_P 1
 
-/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
+/* Maximum number of syntax elements in an instruction.  */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
 
 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
    we can't hash on everything up to the space.  */
 #define CGEN_MNEMONIC_OPERANDS
-/* Maximum number of operands any insn or macro-insn has.  */
-#define CGEN_MAX_INSN_OPERANDS 16
 
 /* Maximum number of fields in an instruction.  */
-#define CGEN_MAX_IFMT_OPERANDS 7
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
 
 /* Enums.  */
 
@@ -93,8 +101,7 @@ typedef enum cr_names {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_M32R
- , MACH_MAX
+  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -102,6 +109,11 @@ typedef enum isa_attr {
   ISA_M32R, ISA_MAX
 } ISA_ATTR;
 
+/* Enum declaration for parallel execution pipeline selection.  */
+typedef enum pipe_attr {
+  PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+} PIPE_ATTR;
+
 /* Number of architecture variants.  */
 #define MAX_ISAS  1
 #define MAX_MACHS ((int) MACH_MAX)
@@ -124,12 +136,13 @@ typedef enum cgen_ifld_attr {
 
 /* Enum declaration for m32r ifield types.  */
 typedef enum ifield_type {
-  M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND
- , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16
- , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16
- , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16
- , M32R_F_DISP24
- , M32R_F_MAX
+  M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
+ , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
+ , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
+ , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
+ , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
+ , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) M32R_F_MAX)
@@ -150,8 +163,8 @@ typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
  , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
- , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW
- , HW_H_LOCK, HW_MAX
+ , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW
+ , HW_H_BBPSW, HW_H_LOCK, HW_MAX
 } CGEN_HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
@@ -174,13 +187,14 @@ typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
+ , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
  , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
  , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
  , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
+#define MAX_OPERANDS 26
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 11
@@ -212,6 +226,7 @@ extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 
 extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
+extern CGEN_KEYWORD m32r_cgen_opval_h_accums;