Add support for intel TSXLDTRK instructions$

[deliverable/binutils-gdb.git] / opcodes / m32r-ibld.c

diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 9ab98cf142dd040beb8493daac5212f1128b6c1e..ddebc32428ec0483c3eeefc168910db133670bc2 100644 (file)
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -480,7 +480,10 @@ extract_normal (CGEN_CPU_DESC cd,
        abort ();
 
       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
-       return 0;
+       {
+         *valuep = 0;
+         return 0;
+       }
 
       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
     }
@@ -723,7 +726,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (4))) + (pc));
         fields->f_disp16 = value;
       }
       break;
@@ -731,7 +734,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (4))) + (pc));
         fields->f_disp24 = value;
       }
       break;
@@ -739,7 +742,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (((pc) & (-4))));
+        value = ((((value) * (4))) + (((pc) & (-4))));
         fields->f_disp8 = value;
       }
       break;