THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
/* -- opc.c */
unsigned int
-m32r_cgen_dis_hash (buf, value)
- const char * buf ATTRIBUTE_UNUSED;
- CGEN_INSN_INT value;
+m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
{
unsigned int x;
-
- if (value & 0xffff0000) /* 32bit instructions */
+
+ if (value & 0xffff0000) /* 32bit instructions. */
value = (value >> 16) & 0xffff;
-
- x = (value>>8) & 0xf0;
+
+ x = (value >> 8) & 0xf0;
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
return x;
-
+
if (x == 0x70 || x == 0xf0)
- return x | ((value>>8) & 0x0f);
-
+ return x | ((value >> 8) & 0x0f);
+
if (x == 0x30)
return x | ((value & 0x70) >> 4);
else
return x | ((value & 0xf0) >> 4);
}
-
+
/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
/* bc $disp8 */
{
-1, "bc8r", "bc", 16,
- { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bc $disp24 */
{
-1, "bc24r", "bc", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bl $disp8 */
{
-1, "bl8r", "bl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bl $disp24 */
{
-1, "bl24r", "bl", 32,
- { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bcl $disp8 */
{
-1, "bcl8r", "bcl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* bcl $disp24 */
{
-1, "bcl24r", "bcl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bnc $disp8 */
{
-1, "bnc8r", "bnc", 16,
- { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bnc $disp24 */
{
-1, "bnc24r", "bnc", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bra $disp8 */
{
-1, "bra8r", "bra", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bra $disp24 */
{
-1, "bra24r", "bra", 32,
- { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bncl $disp8 */
{
-1, "bncl8r", "bncl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* bncl $disp24 */
{
-1, "bncl24r", "bncl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ld $dr,@($sr) */
{
-1, "ld-2", "ld", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ld $dr,@($sr,$slo16) */
{
-1, "ld-d2", "ld", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldb $dr,@($sr) */
{
-1, "ldb-2", "ldb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldb $dr,@($sr,$slo16) */
{
-1, "ldb-d2", "ldb", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldh $dr,@($sr) */
{
-1, "ldh-2", "ldh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldh $dr,@($sr,$slo16) */
{
-1, "ldh-d2", "ldh", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldub $dr,@($sr) */
{
-1, "ldub-2", "ldub", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldub $dr,@($sr,$slo16) */
{
-1, "ldub-d2", "ldub", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* lduh $dr,@($sr) */
{
-1, "lduh-2", "lduh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* lduh $dr,@($sr,$slo16) */
{
-1, "lduh-d2", "lduh", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* pop $dr */
{
-1, "pop", "pop", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldi $dr,$simm8 */
{
-1, "ldi8a", "ldi", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* ldi $dr,$hash$slo16 */
{
-1, "ldi16a", "ldi", 32,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* rac $accd */
{
-1, "rac-d", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* rac $accd,$accs */
{
-1, "rac-ds", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* rach $accd */
{
-1, "rach-d", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* rach $accd,$accs */
{
-1, "rach-ds", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* st $src1,@($src2) */
{
-1, "st-2", "st", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* st $src1,@($src2,$slo16) */
{
-1, "st-d2", "st", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* stb $src1,@($src2) */
{
-1, "stb-2", "stb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* stb $src1,@($src2,$slo16) */
{
-1, "stb-d2", "stb", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* sth $src1,@($src2) */
{
-1, "sth-2", "sth", 16,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* sth $src1,@($src2,$slo16) */
{
-1, "sth-d2", "sth", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* push $src1 */
{
-1, "push", "push", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
};
return CGEN_DIS_HASH (buf, value);
}
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
-set_fields_bitsize (fields, size)
- CGEN_FIELDS *fields;
- int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
This plugs the opcode entries and macro instructions into the cpu table. */
void
-m32r_cgen_init_opcode_table (cd)
- CGEN_CPU_DESC cd;
+m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
sizeof (m32r_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
- CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{
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