/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
- Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2003, 2004, 2005, 2006
- Free Software Foundation, Inc.
+ Copyright (C) 1989-2019 Free Software Foundation, Inc.
- This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of the GNU opcodes library.
- GDB, GAS, and the GNU binutils are free software; you can redistribute
- them and/or modify them under the terms of the GNU General Public
- License as published by the Free Software Foundation; either version
- 1, or (at your option) any later version.
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
- GDB, GAS, and the GNU binutils are distributed in the hope that they
- will be useful, but WITHOUT ANY WARRANTY; without even the implied
- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
- the GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
- along with this file; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#include "sysdep.h"
#include "opcode/m68k.h"
be consecutive. If they aren't, the assembler will bomb at
runtime. */
+/* Format strings consist of pairs of characters. The first describes
+ the type of the operand and the second describes the encoding.
+ include/opcodes/m68k.h describes them in detail. */
+
const struct m68k_opcode m68k_opcodes[] =
{
{"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up },
{"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a },
{"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a },
-{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
-{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
+{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
+{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
{"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a },
{"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a },
{"bgnd", 2, one(0045372), one(0177777), "", cpu32 | fido_a },
-{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa},
+{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa | mcfisa_c},
{"bkpt", 2, one(0044110), one(0177770), "ts", m68010up },
{"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
{"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a },
-{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b},
+{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c},
{"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a },
{"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a },
{"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
{"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
-{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa},
+{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa | mcfisa_c},
{"callm", 4, one(0003300), one(0177700), "#b!s", m68020 },
{"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
{"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
-{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
+{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c },
{"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
-{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
+{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c },
{"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
{"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
/* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
{"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up },
-{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
+{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c },
{"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up },
{"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up },
-{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b },
+{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b | mcfisa_c },
{"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up },
{"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up },
-{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
+{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c },
{"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up },
-{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b },
+{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b | mcfisa_c },
{"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
{"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up },
{"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
{"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
{"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
+{"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a},
+{"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a},
+{"cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a},
+{"cp1nop", 4, two (0177000,0), two (01777477,0170777), "jE", mcfisa_a},
+/* These all have 2 opcode words, but no fixed bits in the second
+ word. We use a leading ' ' in the args string to indicate the
+ extra opcode word. */
+{"cp0ldb", 6, one (0176000), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldb", 6, one (0177000), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ldw", 6, one (0176100), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldw", 6, one (0177100), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ldl", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldl", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ld", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ld", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0stb", 6, one (0176400), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stb", 6, one (0177400), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0stw", 6, one (0176500), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stw", 6, one (0177500), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0stl", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+
{"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
{"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
{"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
{"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
{"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
{"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
-
+
{"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
{"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
{"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
{"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a },
{"extbl", 2, one(0044700), one(0177770), "Ds", m68020up | cpu32 | fido_a | mcfisa_a },
-{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa},
+{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa | mcfisa_c},
/* float stuff starts here */
{"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
{"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
+/* This is the same as `fbf .+2'. */
+{"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat },
+
{"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat },
{"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat },
{"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat },
{"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
{"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up },
-{"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat },
-
{"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
{"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
{"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
{"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a },
{"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a },
-{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b },
+{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b | mcfisa_c },
{"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
-{"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a },
+{"jra", 2, one(0060000), one(0177400), "Bb", m68000up | mcfisa_a },
{"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
{"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
-{"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a },
+{"jbsr", 2, one(0060400), one(0177400), "Bs", m68000up | mcfisa_a },
{"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
{"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a },
{"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
{"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
+{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfemac },
+{"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfemac },
+{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfemac },
+{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0910), "uMumiI", mcfemac },
+{"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0910), "uMumMh", mcfemac },
+{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f10), "uMum", mcfemac },
+
{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
{"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
{"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
-{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
+{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0900), "RMRm", mcfmac },
{"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
{"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
{"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
{"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
+{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfemac },
+{"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfemac },
+{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfemac },
+{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b10), "RMRmiI", mcfemac },
+{"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b10), "RMRmMh", mcfemac },
+{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0910), "RMRm", mcfemac },
+
/* NOTE: The mcf5200 family programmer's reference manual does not
indicate the byte form of the movea instruction is invalid (as it
is on 68000 family cpus). However, experiments on the 5202 yeild
{"moveml", 4, one(0044300), one(0177700), "#w>s", m68000up },
{"moveml", 4, one(0046300), one(0177700), "<sLw", m68000up },
{"moveml", 4, one(0046300), one(0177700), "<s#w", m68000up },
-/* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns. */
-{"moveml", 4, one(0044320), one(0177770), "Lwas", mcfisa_a },
-{"moveml", 4, one(0044320), one(0177770), "#was", mcfisa_a },
-{"moveml", 4, one(0044350), one(0177770), "Lwds", mcfisa_a },
-{"moveml", 4, one(0044350), one(0177770), "#wds", mcfisa_a },
-{"moveml", 4, one(0046320), one(0177770), "asLw", mcfisa_a },
-{"moveml", 4, one(0046320), one(0177770), "as#w", mcfisa_a },
-{"moveml", 4, one(0046350), one(0177770), "dsLw", mcfisa_a },
-{"moveml", 4, one(0046350), one(0177770), "ds#w", mcfisa_a },
+{"moveml", 4, one(0044300), one(0177700), "Lwys", mcfisa_a },
+{"moveml", 4, one(0044300), one(0177700), "#wys", mcfisa_a },
+{"moveml", 4, one(0046300), one(0177700), "ysLw", mcfisa_a },
+{"moveml", 4, one(0046300), one(0177700), "ys#w", mcfisa_a },
{"movepw", 2, one(0000410), one(0170770), "dsDd", m68000up },
{"movepw", 2, one(0000610), one(0170770), "Ddds", m68000up },
{"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a },
{"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a },
{"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a },
-{"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b },
+{"moveb", 2, one(0010074), one(0170077), "#bpd", mcfisa_b | mcfisa_c },
{"movew", 2, one(0030000), one(0170000), "*w%d", m68000up },
{"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
{"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
{"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
-{"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
+{"movew", 2, one(0030074), one(0170077), "#wpd", mcfisa_b | mcfisa_c },
{"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up },
{"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
{"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up },
{"movew", 2, one(0041300), one(0177770), "CsDs", mcfisa_a },
{"movew", 2, one(0042300), one(0177700), ";wCd", m68000up },
-{"movew", 2, one(0042300), one(0177700), "DsCd", mcfisa_a },
+{"movew", 2, one(0042300), one(0177770), "DsCd", mcfisa_a },
{"movew", 4, one(0042374), one(0177777), "#wCd", mcfisa_a },
{"movew", 2, one(0043300), one(0177700), ";wSd", m68000up },
-{"movew", 2, one(0043300), one(0177700), "DsSd", mcfisa_a },
+{"movew", 2, one(0043300), one(0177770), "DsSd", mcfisa_a },
{"movew", 4, one(0043374), one(0177777), "#wSd", mcfisa_a },
{"movel", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a },
{"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a },
{"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a },
{"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a },
-{"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b },
{"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp },
{"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp },
{"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac },
{"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
{"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
{"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
-{"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
+{"move", 2, one(0030074), one(0170077), "#wpd", mcfisa_b | mcfisa_c },
{"move", 2, one(0040300), one(0177700), "Ss$s", m68000up },
{"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
{"move", 2, one(0041300), one(0177700), "Cs$s", m68010up },
{"move", 2, one(0047140), one(0177770), "AsUd", m68000up },
{"move", 2, one(0047150), one(0177770), "UdAs", m68000up },
-{"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b },
-{"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b },
-{"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b },
-{"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b },
-{"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b },
+{"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b | mcfisa_c },
+{"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b | mcfisa_c },
+{"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b | mcfisa_c },
+{"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b | mcfisa_c },
+{"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b | mcfisa_c },
{"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up },
{"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up },
{"msacw", 4, two(0xa000, 0x0300), two(0xf1b0, 0x0900), "uMumMh", mcfmac },
{"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0f00), "uMum", mcfmac },
-{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
-{"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
-{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
+{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
+{"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
+{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
{"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
{"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
{"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
-{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
+{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0900), "RMRm", mcfmac },
{"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
{"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 },
{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 },
{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 },
-{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 },
-{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 },
{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 },
{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 },
{"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 },
+{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "*wX3", m68851 },
+{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "X3%s", m68851 },
{"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 },
{"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 },
{"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up },
{"rtd", 4, one(0047164), one(0177777), "#w", m68010up },
-
+
{"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a },
-
+
{"rtm", 2, one(0003300), one(0177760), "Rs", m68020 },
-
+
{"rtr", 2, one(0047167), one(0177777), "", m68000up },
-
+
{"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a },
-{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b },
+{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c },
{"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up },
{"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up },
+{"stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c },
+
/* Traps have to come before conditional sets, as they have a more
specific opcode. */
{"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a },
{"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a },
{"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a },
-{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b},
+{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b | mcfisa_c},
#define TBL1(name,insn_size,signed,round,size) \
{name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \
{"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a },
{"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a },
+{"wdebugl", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a },
+{"wdebugl", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a },
{"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a },
{"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a },
};
{ "dbhsw", "dbcc", },
{ "dbra", "dbf", },
{ "dbraw", "dbf", },
- { "tdivsl", "divsl", },
+ { "tdivsl", "divsll", },
{ "divs", "divsw", },
{ "divu", "divuw", },
{ "ext", "extw", },
{ "movsw", "movesw", },
{ "mov3q", "mov3ql", },
- { "tdivul", "divul", }, /* For m68k-svr4. */
+ { "tdivul", "divull", }, /* For m68k-svr4. */
{ "fmovb", "fmoveb", },
{ "fsmovb", "fsmoveb", },
{ "fdmovb", "fdmoveb", },
projects / deliverable / binutils-gdb.git / blobdiff