Remove trailing spaces in opcodes

[deliverable/binutils-gdb.git] / opcodes / mep-dis.c

diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index bd3da7a6f12480268ca4b730f5ab7ec2fc6b3193..f2130156563fe959d2e122e57d7832c346d651be 100644 (file)
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -78,7 +78,7 @@ print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
 }
 
 static void
-print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, 
+print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
             CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
             unsigned int flags ATTRIBUTE_UNUSED)
 {
@@ -143,11 +143,11 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
   if (corelength > 0)
     {
       int my_status = 0;
-        
+
       for (i = 0; i < corelength; i++ )
        insnbuf[i] = buf[i];
       cd->isas = & MEP_CORE_ISA;
-        
+
       my_status = print_insn (cd, pc, info, insnbuf, corelength);
       if (my_status != corelength)
        {
@@ -159,7 +159,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
       /* Print the + to indicate that the following copro insn is   */
       /* part of a vliw group.                                      */
       if (copro1length > 0)
-       (*info->fprintf_func) (info->stream, " + "); 
+       (*info->fprintf_func) (info->stream, " + ");
     }
 
   /* Now all that is left to be processed is the coprocessor insns
@@ -171,7 +171,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
   if (copro1length > 0)
     {
       int my_status = 0;
-        
+
       for (i = corelength; i < corelength + copro1length; i++ )
        insnbuf[i - corelength] = buf[i];
 
@@ -190,7 +190,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
          break;
        case 8:
          cd->isas = & MEP_COP64_ISA;
-         break; 
+         break;
        default:
          /* Shouldn't be anything but 16,32,48,64.  */
          break;
@@ -223,7 +223,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
 
       for (i = corelength + copro1length; i < 64; i++)
        insnbuf[i - (corelength + copro1length)] = buf[i];
-      
+
       switch (copro2length)
        {
        case 2:
@@ -236,7 +236,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
          cd->isas = 1 << ISA_EXT_COP1_48;
          break;
        case 8:
-         cd->isas = 1 << ISA_EXT_COP1_64; 
+         cd->isas = 1 << ISA_EXT_COP1_64;
          break;
        default:
          /* Shouldn't be anything but 16,32,48,64.  */
@@ -264,29 +264,29 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
     return status;
 }
 
-/* The two functions mep_examine_vliw[32,64]_insns are used find out 
-   which vliw combinaion (16 bit core with 48 bit copro, 32 bit core 
-   with 32 bit copro, etc.) is present.  Later on, when internally   
-   parallel coprocessors are handled, only these functions should    
-   need to be changed.                                               
+/* The two functions mep_examine_vliw[32,64]_insns are used find out
+   which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
+   with 32 bit copro, etc.) is present.  Later on, when internally
+   parallel coprocessors are handled, only these functions should
+   need to be changed.
+
+   At this time only the following combinations are supported:
 
-   At this time only the following combinations are supported: 
-   
    VLIW32 Mode:
    16 bit core insn (core) and 16 bit coprocessor insn (cop1)
    32 bit core insn (core)
    32 bit coprocessor insn (cop1)
    Note: As of this time, I do not believe we have enough information
          to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
-         no 16 bit coprocessor insns have been specified.  
+         no 16 bit coprocessor insns have been specified.
 
    VLIW64 Mode:
    16 bit core insn (core) and 48 bit coprocessor insn (cop1)
    32 bit core insn (core) and 32 bit coprocessor insn (cop1)
    64 bit coprocessor insn (cop1)
-  
+
    The framework for an internally parallel coprocessor is also
-   present (2nd coprocessor insn is cop2), but at this time it 
+   present (2nd coprocessor insn is cop2), but at this time it
    is not used.  This only appears to be valid in VLIW64 mode.  */
 
 static int
@@ -297,9 +297,9 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];  
+  bfd_byte buf[CGEN_MAX_INSN_SIZE];
   char indicator16[1];
-  char indicatorcop32[2]; 
+  char indicatorcop32[2];
 
   /* At this time we're not supporting internally parallel coprocessors,
      so cop2buflength will always be 0.  */
@@ -1189,7 +1189,7 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
   }
 }
 
-cgen_print_fn * const mep_cgen_print_handlers[] = 
+cgen_print_fn * const mep_cgen_print_handlers[] =
 {
   print_insn_normal,
 };
@@ -1379,7 +1379,7 @@ print_insn (CGEN_CPU_DESC cd,
       int length;
       unsigned long insn_value_cropped;
 
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
       /* Not needed as insn shouldn't be in hash lists if not supported.  */
       /* Supported by this cpu?  */
       if (! mep_cgen_insn_supported (cd, insn))
@@ -1397,7 +1397,7 @@ print_insn (CGEN_CPU_DESC cd,
          relevant part from the buffer. */
       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
          (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
-       insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
+       insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
                                           info->endian == BFD_ENDIAN_BIG);
       else
        insn_value_cropped = insn_value;
@@ -1516,7 +1516,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
   arch = info->arch;
   if (arch == bfd_arch_unknown)
     arch = CGEN_BFD_ARCH;
-   
+
   /* There's no standard way to compute the machine or isa number
      so we leave it to the target.  */
 #ifdef CGEN_COMPUTE_MACH
@@ -1557,7 +1557,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
              break;
            }
        }
-    } 
+    }
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)