ubsan: aarch64: left shift cannot be represented in type 'int64_t'

[deliverable/binutils-gdb.git] / opcodes / micromips-opc.c

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index d8edd282f20c8473477326f6917a9d9d7af91fab..439d4d4fc77c2137dcc2cea7debc6c1b31fb7f65 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -1,5 +1,5 @@
 /* micromips-opc.c.  microMIPS opcode table.
-   Copyright (C) 2008-2017 Free Software Foundation, Inc.
+   Copyright (C) 2008-2019 Free Software Foundation, Inc.
    Contributed by Chao-ying Fu, MIPS Technologies, Inc.
 
    This file is part of the GNU opcodes library.
@@ -280,6 +280,10 @@ decode_micromips_operand (const char *p)
 #define MSA     ASE_MSA
 #define MSA64   ASE_MSA64
 
+/* eXtended Physical Address (XPA) support.  */
+#define XPA    ASE_XPA
+#define XPAVZ  ASE_XPA_VIRT
+
 const struct mips_opcode micromips_opcodes[] =
 {
 /* These instructions appear first so that the disassembler will find
@@ -835,6 +839,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"mfc2",               "t,G",          0x00004d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
 {"mfgc0",              "t,G",          0x000004fc, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x000004fc, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
+{"mfhc0",              "t,G",          0x000000f4, 0xfc00ffff, WR_1|RD_C0,             0,              0,              XPA,    0 },
+{"mfhc0",              "t,G,H",        0x000000f4, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              XPA,    0 },
+{"mfhgc0",             "t,G",          0x000004f4, 0xfc00ffff, WR_1|RD_C0,             0,              0,              XPAVZ,  0 },
+{"mfhgc0",             "t,G,H",        0x000004f4, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              XPAVZ,  0 },
 {"mfhc1",              "t,S",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
 {"mfhc1",              "t,G",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
 {"mfhc2",              "t,G",          0x00008d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
@@ -881,6 +889,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"mtc2",               "t,G",          0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"mtgc0",              "t,G",          0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
+{"mthc0",              "t,G",          0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              XPA,    0 },
+{"mthc0",              "t,G,H",        0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              XPA,    0 },
+{"mthgc0",             "t,G",          0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              XPAVZ,  0 },
+{"mthgc0",             "t,G,H",        0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              XPAVZ,  0 },
 {"mthc1",              "t,S",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
 {"mthc1",              "t,G",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
 {"mthc2",              "t,G",          0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },