/* micromips-opc.c. microMIPS opcode table.
- Copyright (C) 2008-2015 Free Software Foundation, Inc.
+ Copyright (C) 2008-2021 Free Software Foundation, Inc.
Contributed by Chao-ying Fu, MIPS Technologies, Inc.
This file is part of the GNU opcodes library.
case 'y': MAPPED_REG (0, 0, GP, reg_31_map);
case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
- case 'A': INT_ADJ (7, 0, 63, 2, FALSE); /* (-64 .. 63) << 2 */
- case 'B': MAPPED_INT (3, 1, int_b_map, FALSE);
- case 'C': MAPPED_INT (4, 0, int_c_map, TRUE);
+ case 'A': INT_ADJ (7, 0, 63, 2, false); /* (-64 .. 63) << 2 */
+ case 'B': MAPPED_INT (3, 1, int_b_map, false);
+ case 'C': MAPPED_INT (4, 0, int_c_map, true);
case 'D': BRANCH (10, 0, 1);
case 'E': BRANCH (7, 0, 1);
case 'F': HINT (4, 0);
- case 'G': INT_ADJ (4, 0, 14, 0, FALSE); /* (-1 .. 14) */
- case 'H': INT_ADJ (4, 0, 15, 1, FALSE); /* (0 .. 15) << 1 */
- case 'I': INT_ADJ (7, 0, 126, 0, FALSE); /* (-1 .. 126) */
- case 'J': INT_ADJ (4, 0, 15, 2, FALSE); /* (0 .. 15) << 2 */
- case 'L': INT_ADJ (4, 0, 15, 0, FALSE); /* (0 .. 15) */
- case 'M': INT_ADJ (3, 1, 8, 0, FALSE); /* (1 .. 8) */
+ case 'G': INT_ADJ (4, 0, 14, 0, false); /* (-1 .. 14) */
+ case 'H': INT_ADJ (4, 0, 15, 1, false); /* (0 .. 15) << 1 */
+ case 'I': INT_ADJ (7, 0, 126, 0, false); /* (-1 .. 126) */
+ case 'J': INT_ADJ (4, 0, 15, 2, false); /* (0 .. 15) << 2 */
+ case 'L': INT_ADJ (4, 0, 15, 0, false); /* (0 .. 15) */
+ case 'M': INT_ADJ (3, 1, 8, 0, false); /* (1 .. 8) */
case 'N': SPECIAL (2, 4, LWM_SWM_LIST);
case 'O': HINT (4, 0);
- case 'P': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
- case 'Q': INT_ADJ (23, 0, 4194303, 2, FALSE);
+ case 'P': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */
+ case 'Q': INT_ADJ (23, 0, 4194303, 2, false);
/* (-4194304 .. 4194303) */
- case 'U': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
- case 'W': INT_ADJ (6, 1, 63, 2, FALSE); /* (0 .. 63) << 2 */
+ case 'U': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */
+ case 'W': INT_ADJ (6, 1, 63, 2, false); /* (0 .. 63) << 2 */
case 'X': SINT (4, 1);
case 'Y': SPECIAL (9, 1, ADDIUSP_INT);
case 'Z': UINT (0, 0); /* 0 only */
switch (p[1])
{
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
- case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */
- case 'C': MSB (5, 11, 1, FALSE, 32); /* (1 .. 32), 32-bit op */
+ case 'B': MSB (5, 11, 1, true, 32); /* (1 .. 32), 32-bit op */
+ case 'C': MSB (5, 11, 1, false, 32); /* (1 .. 32), 32-bit op */
case 'E': BIT (5, 6, 32); /* (32 .. 63) */
- case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */
- case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
- case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
+ case 'F': MSB (5, 11, 33, true, 64); /* (33 .. 64), 64-bit op */
+ case 'G': MSB (5, 11, 33, false, 64); /* (33 .. 64), 64-bit op */
+ case 'H': MSB (5, 11, 1, false, 64); /* (1 .. 32), 64-bit op */
case 'J': HINT (10, 16);
- case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
- case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
- case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
- case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */
+ case 'T': INT_ADJ (10, 16, 511, 0, false); /* (-512 .. 511) << 0 */
+ case 'U': INT_ADJ (10, 16, 511, 1, false); /* (-512 .. 511) << 1 */
+ case 'V': INT_ADJ (10, 16, 511, 2, false); /* (-512 .. 511) << 2 */
+ case 'W': INT_ADJ (10, 16, 511, 3, false); /* (-512 .. 511) << 3 */
case 'd': REG (5, 6, MSA);
case 'e': REG (5, 11, MSA);
are accepted as 64-bit microMIPS ISA. */
#define I1 INSN_ISA1
#define I3 INSN_ISA3
+#define I36 INSN_ISA32R5
/* MIPS DSP ASE support. */
#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
#define MSA ASE_MSA
#define MSA64 ASE_MSA64
+/* eXtended Physical Address (XPA) support. */
+#define XPA ASE_XPA
+#define XPAVZ ASE_XPA_VIRT
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 },
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 },
{"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
+{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */
{"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */
{"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */
-{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */
{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */
{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */
+/* BC is next to B so that we easily find it when converting a normal
+ branch to a compact one. */
+{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */
{"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */
{"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */
-{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */
-
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 },
{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
{"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */
{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */
{"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
+/* BEQZC is next to BEQ so that we easily find it when converting a normal
+ branch to a compact one. */
+{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 },
{"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
{"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */
{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */
{"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
+/* BNEZC is next to BNE so that we easily find it when converting a normal
+ branch to a compact one. */
+{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 },
{"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
{"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 },
{"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 },
{"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 },
+{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 },
{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 },
-{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 },
-/* This macro is after the real instruction so that it only matches with
- -minsn32. */
-{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 },
{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */
{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */
{"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */
assembler, but will never match user input (because the line above
will match first). */
{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 },
+/* JRC is close to JR and J so that we easily find it when converting
+ a normal jump to a compact one. */
+{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 },
+/* This macro is after the real instruction so that it only matches with
+ -minsn32. */
+{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 },
{"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
{"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 },
{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
+{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
+{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
+{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
+{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */
{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 },
{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 },
-{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
-{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
-{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
-{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
-{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
+{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
{"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
{"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 },
{"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 },
projects / deliverable / binutils-gdb.git / blobdiff