ubsan: alpha-vma: timeout
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
index b151baea0c29bba1d590299f057e94eb272d3200..5270aeefa80e50cc042a5b89b212f9571a8c7501 100644 (file)
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2017 Free Software Foundation, Inc.
+   Copyright (C) 1993-2020 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -139,6 +139,7 @@ decode_mips_operand (const char *p)
        case '\'': BRANCH (26, 0, 2);
        case '"': BRANCH (21, 0, 2);
        case ';': SPECIAL (10, 16, SAME_RS_RT);
+       case '\\': BIT (2, 8, 0);               /* (0 .. 3) */
        }
       break;
 
@@ -307,7 +308,6 @@ decode_mips_operand (const char *p)
 
 #define IL2E    (INSN_LOONGSON_2E)
 #define IL2F    (INSN_LOONGSON_2F)
-#define IL3A    (INSN_LOONGSON_3A)
 
 #define P3     INSN_4650
 #define L1     INSN_4010
@@ -392,6 +392,7 @@ decode_mips_operand (const char *p)
 
 /* MIPS Enhanced VA Scheme.  */
 #define EVA    ASE_EVA
+#define EVAR6  ASE_EVA_R6
 
 /* TLB invalidate instruction support.  */
 #define TLBINV ASE_EVA
@@ -402,6 +403,26 @@ decode_mips_operand (const char *p)
 
 /* eXtended Physical Address (XPA) support.  */
 #define XPA     ASE_XPA
+#define XPAVZ  ASE_XPA_VIRT
+
+/* Cyclic redundancy check instruction (CRC) support.  */
+#define CRC    ASE_CRC
+#define CRC64  ASE_CRC64
+
+/* Global INValidate (GINV) support.  */
+#define GINV   ASE_GINV
+
+/* Loongson MultiMedia extensions Instructions (MMI) support.  */
+#define LMMI   ASE_LOONGSON_MMI
+
+/* Loongson Content Address Memory (CAM) support.  */
+#define LCAM   ASE_LOONGSON_CAM
+
+/* Loongson EXTensions (EXT) instructions support.  */
+#define LEXT   ASE_LOONGSON_EXT
+
+/* Loongson EXTensions R2 (EXT2) instructions support.  */
+#define LEXT2  ASE_LOONGSON_EXT2
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -444,63 +465,67 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lapc",               "s,-A",         0xec000000, 0xfc180000, WR_1,                   RD_pc,          I37,            0,      0 },
 {"la",                 "t,A(b)",       0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 
-/* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
+/* Loongson specific instructions.  Loongson gs464 (aka loongson3a) redefines the Coprocessor 2
    instructions.  Put them here so that disassembler will find them first.
    The assemblers uses a hash table based on the instruction name anyhow.  */
-{"campi",              "d,s",          0x70000075, 0xfc1f07ff, WR_1|RD_2,              0,              IL3A,           0,      0 },
-{"campv",              "d,s",          0x70000035, 0xfc1f07ff, WR_1|RD_2,              0,              IL3A,           0,      0 },
-{"camwi",              "d,s,t",        0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
-{"ramri",              "d,s",          0x700000f5, 0xfc1f07ff, WR_1|RD_2,              0,              IL3A,           0,      0 },
-{"gsle",               "s,t",          0x70000026, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
-{"gsgt",               "s,t",          0x70000027, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
-{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gssble",             "t,b,d",        0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssbgt",             "t,b,d",        0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsshle",             "t,b,d",        0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsshgt",             "t,b,d",        0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswle",             "t,b,d",        0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswgt",             "t,b,d",        0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdle",             "t,b,d",        0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdgt",             "t,b,d",        0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsswlec1",           "T,b,d",        0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswgtc1",           "T,b,d",        0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdlec1",           "T,b,d",        0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdgtc1",           "T,b,d",        0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsswlc1",            "T,+a(b)",      0xe8000004, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gsswrc1",            "T,+a(b)",      0xe8000005, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gssdlc1",            "T,+a(b)",      0xe8000006, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gssdrc1",            "T,+a(b)",      0xe8000007, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssbx",              "t,+b(b,d)",    0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gsshx",              "t,+b(b,d)",    0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gsswx",              "t,+b(b,d)",    0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gssdx",              "t,+b(b,d)",    0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsswxc1",            "T,+b(b,d)",    0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gssdxc1",            "T,+b(b,d)",    0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssq",               "+z,t,+c(b)",   0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssqc1",             "+Z,T,+c(b)",   0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
+{"campi",              "d,s",          0x70000075, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LCAM,   0 },
+{"campv",              "d,s",          0x70000035, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LCAM,   0 },
+{"camwi",              "d,s,t",        0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3,         0,              0,              LCAM,   0 },
+{"ramri",              "d,s",          0x700000f5, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LCAM,   0 },
+{"gsle",               "s,t",          0x70000026, 0xfc00ffff, RD_1|RD_2,              0,              0,              LEXT,   0 },
+{"gsgt",               "s,t",          0x70000027, 0xfc00ffff, RD_1|RD_2,              0,              0,              LEXT,   0 },
+{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gssble",             "t,b,d",        0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssbgt",             "t,b,d",        0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsshle",             "t,b,d",        0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsshgt",             "t,b,d",        0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswle",             "t,b,d",        0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswgt",             "t,b,d",        0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdle",             "t,b,d",        0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdgt",             "t,b,d",        0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsswlec1",           "T,b,d",        0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswgtc1",           "T,b,d",        0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdlec1",           "T,b,d",        0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdgtc1",           "T,b,d",        0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsswlc1",            "T,+a(b)",      0xe8000004, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gsswrc1",            "T,+a(b)",      0xe8000005, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gssdlc1",            "T,+a(b)",      0xe8000006, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gssdrc1",            "T,+a(b)",      0xe8000007, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssbx",              "t,+b(b,d)",    0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gsshx",              "t,+b(b,d)",    0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gsswx",              "t,+b(b,d)",    0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gssdx",              "t,+b(b,d)",    0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsswxc1",            "T,+b(b,d)",    0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gssdxc1",            "T,+b(b,d)",    0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssq",               "+z,t,+c(b)",   0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssqc1",             "+Z,T,+c(b)",   0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              0,              LEXT,   0 },
+{"cto",                        "d,s",          0x70000062, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },
+{"ctz",                        "d,s",          0x70000022, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },
+{"dcto",               "d,s",          0x700000e2, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },
+{"dctz",               "d,s",          0x700000a2, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },
 
 /* R5900 VU0 Macromode instructions. */
 {"vabs",               "+7+K,+6+K",      0x4a0001fd, 0xfe0007ff,       CP,             VU0CH,          VU0,            0,      0 },
@@ -641,9 +666,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"aclr",               "\\,~(b)",      0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS,        0,              0,              MC,     0 },
 {"aclr",               "\\,A(b)",      0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,              MC,     0 },
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"add",                        "D,S,T",        0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"add.s",              "D,V,T",        0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"add.d",              "D,V,T",        0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"add.ob",             "X,Y,Q",        0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -664,7 +689,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",               "d,v,t",        0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"addu",               "t,r,I",        0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"addu",               "D,S,T",        0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"alni.ob",            "X,Y,Z,O",      0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"alni.ob",            "D,S,T,%",      0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"alni.qh",            "X,Y,Z,O",      0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -674,7 +699,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and",                        "d,v,t",        0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"and",                        "t,r,I",        0,    (int) M_AND_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"and",                        "D,S,T",        0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"and.ob",             "X,Y,Q",        0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"and.ob",             "D,S,Q",        0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"and.qh",             "X,Y,Q",        0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -990,9 +1015,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cvt.pw.ps",          "D,S",          0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              0,              M3D,    0 },
 {"dabs",               "d,v",          0,    (int) M_DABS,     INSN_MACRO,             0,              I3,             0,      0 },
 {"dadd",               "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dadd",               "D,S,T",        0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      I69 },
 {"daddiu",             "t,r,j",        0x64000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
 {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
@@ -1132,25 +1157,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",               "d,w,>",        0x0000003c, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsll32 */
 {"dsll",               "d,w,<",        0x00000038, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsll",               "D,S,T",        0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrav",              "d,t,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsra32",             "d,w,<",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "d,w,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrav */
 {"dsra",               "d,w,>",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsra32 */
 {"dsra",               "d,w,<",        0x0000003b, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "D,S,T",        0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrlv",              "d,t,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsrl32",             "d,w,<",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "d,w,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrlv */
 {"dsrl",               "d,w,>",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsrl32 */
 {"dsrl",               "d,w,<",        0x0000003a, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "D,S,T",        0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsub",               "d,v,t",        0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dsub",               "D,S,T",        0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsubu",              "d,v,t",        0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"dvpe",               "",             0x41600001, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
@@ -1276,6 +1301,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lld",                        "t,+j(b)",      0x7c000037, 0xfc00007f, WR_1|RD_3|LM,           0,              I69,            0,      0 },
 {"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      EE|I69 },
 {"lld",                        "t,A(b)",       0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
+{"lldp",               "t,d,s",        0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              I69,            0,      0 },
+{"lldp",               "t,d,A(b)",     0,    (int) M_LLDP_AB,  INSN_MACRO,             0,              I69,            0,      0 },
+{"llwp",               "t,d,s",        0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              I37,            0,      0 },
+{"llwp",               "t,d,A(b)",     0,    (int) M_LLWP_AB,  INSN_MACRO,             0,              I37,            0,      0 },
 {"lq",                 "t,o(b)",       0x78000000, 0xfc000000, WR_1|RD_3|LM,           0,              MMI,            0,      0 },
 {"lq",                 "t,A(b)",       0,    (int) M_LQ_AB,    INSN_MACRO,             0,              MMI,            0,      0 },
 {"lqc2",               "+7,o(b)",      0xd8000000, 0xfc000000, RD_3|WR_C2|LM,          0,              EE,             0,      0 },
@@ -1390,10 +1419,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I32,            0,      0 },
 {"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
-{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
-{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
-{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
-{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
+{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              XPA,    0 },
+{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              XPA,    0 },
+{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              XPAVZ,  0 },
+{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              XPAVZ,  0 },
 {"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
 {"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
 {"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
@@ -1427,7 +1456,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.s",             "D,S,N",        0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"movf.ps",            "D,S,N",        0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  I37 },
-{"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F|IL3A, 0,      0 },
+{"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F,      LEXT,   0 },
 {"ffc",                        "d,v",          0x0000000b, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
 {"movn.d",             "D,S,t",        0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
 {"movn.l",             "D,S,t",        0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -1488,10 +1517,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I32,            0,      0 },
 {"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT,  0 },
-{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
-{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
-{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
-{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPA,    0 },
+{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPA,    0 },
+{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPAVZ,  0 },
+{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPAVZ,  0 },
 {"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
 {"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
 {"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
@@ -1619,7 +1648,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",                        "d,v,t",        0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"nor",                        "t,r,I",        0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"nor",                        "D,S,T",        0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"nor.ob",             "X,Y,Q",        0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"nor.ob",             "D,S,Q",        0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"nor.qh",             "X,Y,Q",        0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1627,7 +1656,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",                 "d,v,t",        0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"or",                 "t,r,I",        0,    (int) M_OR_I,     INSN_MACRO,             0,              I1,             0,      0 },
 {"or",                 "D,S,T",        0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"or.ob",              "X,Y,Q",        0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"or.ob",              "D,S,Q",        0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"or.qh",              "X,Y,Q",        0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1757,6 +1786,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"remu",               "d,v,t",        0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1,             0,      I37 },
 {"remu",               "d,v,I",        0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1,             0,      I37 },
 {"rdhwr",              "t,K",          0x7c00003b, 0xffe007ff, WR_1,                   0,              I33,            0,      0 },
+{"rdhwr",              "t,K,+O",       0x7c00003b, 0xffe0063f, WR_1,                   0,              I37,            0,      0 },
 {"rdpgpr",             "d,w",          0x41400000, 0xffe007ff, WR_1,                   0,              I33,            0,      0 },
 /* rfe is moved below as it now conflicts with tlbgp */
 {"rnas.qh",            "X,Q",          0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D,         RD_MACC,        0,              MX,     0 },
@@ -1806,6 +1836,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"scd",                        "t,+j(b)",      0x7c000027, 0xfc00007f, MOD_1|RD_3|SM,          0,              I69,            0,      0 },
 {"scd",                        "t,o(b)",       0xf0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I3,             0,      EE|I69 },
 {"scd",                        "t,A(b)",       0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
+{"scdp",               "t,d,s",        0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              I69,            0,      0 },
+{"scdp",               "t,d,A(b)",     0,    (int) M_SCDP_AB,  INSN_MACRO,             0,              I69,            0,      0 },
+{"scwp",               "t,d,s",        0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              I37,            0,      0 },
+{"scwp",               "t,d,A(b)",     0,    (int) M_SCWP_AB,  INSN_MACRO,             0,              I37,            0,      0 },
 /* The macro has to be first to handle o32 correctly.  */
 {"sd",                 "t,A(b)",       0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sd",                 "t,o(b)",       0xfc000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      0 },
@@ -1840,7 +1874,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"seq",                        "d,v,t",        0,    (int) M_SEQ,      INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "d,v,I",        0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "S,T",          0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"seqi",               "t,r,+Q",       0x7000002e, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"sge",                        "d,v,t",        0,    (int) M_SGE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sge",                        "d,v,I",        0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1866,33 +1900,33 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.repa.qh",       "X,Y,Z",        0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.repb.qh",       "X,Y,Z",        0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.upsl.ob",       "X,Y,Z",        0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
-{"sigrie",             "u",            0x41700000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
+{"sigrie",             "u",            0x04170000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
 {"sle",                        "d,v,t",        0,    (int) M_SLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "d,v,I",        0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "S,T",          0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sleu",               "d,v,t",        0,    (int) M_SLEU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "d,v,I",        0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "S,T",          0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sllv",               "d,t,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sll",                        "d,w,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* sllv */
 {"sll",                        "d,w,<",        0x00000000, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sll",                        "D,S,T",        0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sll.ob",             "X,Y,Q",        0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"sll.ob",             "D,S,Q",        0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"sll.qh",             "X,Y,Q",        0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"slt",                        "d,v,t",        0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"slt",                        "d,v,I",        0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"slt",                        "S,T",          0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"slti",               "t,r,j",        0x28000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltiu",              "t,r,j",        0x2c000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltu",               "d,v,t",        0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sltu",               "d,v,I",        0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sltu",               "S,T",          0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sne",                        "d,v,t",        0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 {"sne",                        "d,v,t",        0,    (int) M_SNE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sne",                        "d,v,I",        0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1908,22 +1942,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",                        "d,w,s",        0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srav */
 {"sra",                        "d,w,<",        0x00000003, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sra",                        "D,S,T",        0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sra.qh",             "X,Y,Q",        0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"srlv",               "d,t,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"srl",                        "d,w,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srlv */
 {"srl",                        "d,w,<",        0x00000002, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"srl",                        "D,S,T",        0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"srl.ob",             "X,Y,Q",        0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"srl.ob",             "D,S,Q",        0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"srl.qh",             "X,Y,Q",        0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 /* ssnop is at the start of the table.  */
 {"standby",            "",             0x42000021, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"sub",                        "d,v,t",        0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sub",                        "D,S,T",        0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"sub.d",              "D,V,T",        0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"sub.s",              "D,V,T",        0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"sub.ob",             "X,Y,Q",        0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -1939,7 +1973,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",               "d,v,t",        0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"subu",               "d,v,I",        0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"subu",               "D,S,T",        0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"suspend",            "",             0x42000022, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      I37},
 {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
@@ -2060,7 +2094,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",                        "d,v,t",        0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"xor",                        "t,r,I",        0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"xor",                        "D,S,T",        0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"xor.ob",             "X,Y,Q",        0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"xor.ob",             "D,S,Q",        0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"xor.qh",             "X,Y,Q",        0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -2426,174 +2460,174 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",             "d,s,t",        0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"mult.g",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmult",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmult",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"multu.g",            "d,s,t",        0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"multu.g",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmultu",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmultu",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmult.g",            "d,s,t",        0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmult.g",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmult",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmult",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmultu.g",           "d,s,t",        0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmultu.g",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmultu",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmultu",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"div.g",              "d,s,t",        0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"div.g",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdiv",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdiv",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"divu.g",             "d,s,t",        0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"divu.g",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdivu",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdivu",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"ddiv.g",             "d,s,t",        0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"ddiv.g",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsddiv",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsddiv",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"ddivu.g",            "d,s,t",        0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"ddivu.g",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsddivu",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsddivu",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"mod.g",              "d,s,t",        0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"mod.g",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmod",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmod",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"modu.g",             "d,s,t",        0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"modu.g",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmodu",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmodu",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmod.g",             "d,s,t",        0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmod.g",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmod",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmod",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmodu.g",            "d,s,t",        0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmodu.g",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"packsshb",           "D,S,T",        0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packsswh",           "D,S,T",        0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packushb",           "D,S,T",        0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "D,S,T",        0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "d,s,t",        0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddh",              "D,S,T",        0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"paddh",              "d,s,t",        0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
-{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "D,S,T",        0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "d,s,t",        0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddd",              "D,S,T",        0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "D,S,T",        0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "d,s,t",        0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddsh",             "D,S,T",        0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsh",             "d,s,t",        0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddusb",            "D,S,T",        0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddush",            "D,S,T",        0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pandn",              "D,S,T",        0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgb",              "D,S,T",        0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgh",              "D,S,T",        0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqb",            "D,S,T",        0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqh",            "D,S,T",        0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqw",            "D,S,T",        0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtb",            "D,S,T",        0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgth",            "D,S,T",        0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtw",            "D,S,T",        0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pextrh",             "D,S,T",        0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_0",           "D,S,T",        0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_1",           "D,S,T",        0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_2",           "D,S,T",        0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_3",           "D,S,T",        0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaddhw",            "D,S,T",        0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxsh",             "D,S,T",        0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxub",             "D,S,T",        0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminsh",             "D,S,T",        0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminub",             "D,S,T",        0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmovmskb",           "D,S",          0x46a00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pmulhuh",            "D,S,T",        0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmulhh",             "D,S,T",        0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmullh",             "D,S,T",        0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmuluw",             "D,S,T",        0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pasubub",            "D,S,T",        0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"biadd",              "D,S",          0x46800005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pshufh",             "D,S,T",        0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "D,S,T",        0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "d,t,<",        0x70000034, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psllw",              "D,S,T",        0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllw",              "d,t,<",        0x7000003c, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrah",              "D,S,T",        0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrah",              "d,t,<",        0x70000037, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psraw",              "D,S,T",        0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psraw",              "d,t,<",        0x7000003f, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlh",              "D,S,T",        0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlh",              "d,t,<",        0x70000036, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlw",              "D,S,T",        0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlw",              "d,t,<",        0x7000003e, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psubb",              "D,S,T",        0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubb",              "d,s,t",        0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubh",              "D,S,T",        0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubh",              "d,s,t",        0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubw",              "D,S,T",        0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubw",              "d,s,t",        0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubd",              "D,S,T",        0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "D,S,T",        0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "d,s,t",        0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubsh",             "D,S,T",        0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsh",             "d,s,t",        0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubusb",            "D,S,T",        0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubush",            "D,S,T",        0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhbh",          "D,S,T",        0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhhw",          "D,S,T",        0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhwd",          "D,S,T",        0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklbh",          "D,S,T",        0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklhw",          "D,S,T",        0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklwd",          "D,S,T",        0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sequ",               "S,T",          0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 /* MIPS Enhanced VA Scheme */
 {"lbue",               "t,+j(b)",      0x7c000028, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbue",               "t,A(b)",       0,    (int) M_LBUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
@@ -2605,6 +2639,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lhe",                        "t,A(b)",       0,    (int) M_LHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"lle",                        "t,+j(b)",      0x7c00002e, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lle",                        "t,A(b)",       0,    (int) M_LLE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
+{"llwpe",              "t,d,s",        0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              0,              EVAR6,  0 },
+{"llwpe",              "t,d,A(b)",     0,    (int) M_LLWPE_AB, INSN_MACRO,             0,              0,              EVAR6,  0 },
 {"lwe",                        "t,+j(b)",      0x7c00002f, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwe",                        "t,A(b)",       0,    (int) M_LWE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    I37 },
@@ -2615,6 +2651,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sbe",                        "t,A(b)",       0,    (int) M_SBE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"sce",                        "t,+j(b)",      0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM,          0,              0,              EVA,    0 },
 {"sce",                        "t,A(b)",       0,    (int) M_SCE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
+{"scwpe",              "t,d,s",        0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              0,              EVAR6,  0 },
+{"scwpe",              "t,d,A(b)",     0,    (int) M_SCWPE_AB, INSN_MACRO,             0,              0,              EVAR6,  0 },
 {"she",                        "t,+j(b)",      0x7c00001d, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
 {"she",                        "t,A(b)",       0,    (int) M_SHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"swe",                        "t,+j(b)",      0x7c00001f, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
@@ -3157,6 +3195,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|CM,                0,              0,              MSA,    0 },
 {"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|CM,                0,              0,              MSA,    0 },
 {"move.v",             "+d,+e",        0x78be0019, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
+{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            MSA,    0 },
+{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I69,            MSA64,  0 },
 
 /* interAptiv MR2 instruction extensions.  */
 {"restore",            "-m",           0x7000001f, 0xfc00603f, WR_31|NODS,             MOD_SP,         IAMR2,          0,      0 },
@@ -3227,13 +3267,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"udi15",              "s,t,+2",       0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "s,+3",         0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "+4",           0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
-{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            MSA,    0 },
-{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I69,            MSA64,  0 },
-/* MIPS r6.  */
 
+/* MIPS r6.  */
 {"aui",                        "t,s,u",        0x3c000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
 {"auipc",              "s,u",          0xec1e0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
-{"daui",               "t,s,u",        0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
+{"daui",               "t,-s,u",       0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
 {"dahi",               "s,-d,u",       0x04060000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },
 {"dati",               "s,-d,u",       0x041e0000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },
 
@@ -3346,6 +3384,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"aluipc",             "s,u",          0xec1f0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
 
+/* MIPS cyclic redundancy check (CRC) ASE.  */
+{"crc32b",             "t,s,-d",       0x7c00000f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32h",             "t,s,-d",       0x7c00004f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32w",             "t,s,-d",       0x7c00008f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32d",             "t,s,-d",       0x7c0000cf, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC64,  0 },
+{"crc32cb",            "t,s,-d",       0x7c00010f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32ch",            "t,s,-d",       0x7c00014f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32cw",            "t,s,-d",       0x7c00018f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32cd",            "t,s,-d",       0x7c0001cf, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC64,  0 },
+
+/* MIPS Global INValidate (GINV) ASE.  */
+{"ginvi",              "s",            0x7c00003d, 0xfc1fffff, RD_1,                   0,              0,              GINV,   0 },
+{"ginvt",              "s,+\\",        0x7c0000bd, 0xfc1ffcff, RD_1,                   0,              0,              GINV,   0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
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