[MIPS] Add load-link, store-conditional paired instructions

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 91f60275f31da7092549097877e2384376bfa845..8db29522aa6e981276e7d5dd4ede6e2ff247fa01 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1300,6 +1300,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lld",                        "t,+j(b)",      0x7c000037, 0xfc00007f, WR_1|RD_3|LM,           0,              I69,            0,      0 },
 {"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      EE|I69 },
 {"lld",                        "t,A(b)",       0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
+{"lldp",               "t,d,s",        0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              I69,            0,      0 },
+{"lldp",               "t,d,A(b)",     0,    (int) M_LLDP_AB,  INSN_MACRO,             0,              I69,            0,      0 },
+{"llwp",               "t,d,s",        0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              I37,            0,      0 },
+{"llwp",               "t,d,A(b)",     0,    (int) M_LLWP_AB,  INSN_MACRO,             0,              I37,            0,      0 },
 {"lq",                 "t,o(b)",       0x78000000, 0xfc000000, WR_1|RD_3|LM,           0,              MMI,            0,      0 },
 {"lq",                 "t,A(b)",       0,    (int) M_LQ_AB,    INSN_MACRO,             0,              MMI,            0,      0 },
 {"lqc2",               "+7,o(b)",      0xd8000000, 0xfc000000, RD_3|WR_C2|LM,          0,              EE,             0,      0 },
@@ -1831,6 +1835,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"scd",                        "t,+j(b)",      0x7c000027, 0xfc00007f, MOD_1|RD_3|SM,          0,              I69,            0,      0 },
 {"scd",                        "t,o(b)",       0xf0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I3,             0,      EE|I69 },
 {"scd",                        "t,A(b)",       0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
+{"scdp",               "t,d,s",        0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              I69,            0,      0 },
+{"scdp",               "t,d,A(b)",     0,    (int) M_SCDP_AB,  INSN_MACRO,             0,              I69,            0,      0 },
+{"scwp",               "t,d,s",        0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              I37,            0,      0 },
+{"scwp",               "t,d,A(b)",     0,    (int) M_SCWP_AB,  INSN_MACRO,             0,              I37,            0,      0 },
 /* The macro has to be first to handle o32 correctly.  */
 {"sd",                 "t,A(b)",       0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sd",                 "t,o(b)",       0xfc000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      0 },