ubsan: alpha-vma: timeout

[deliverable/binutils-gdb.git] / opcodes / mips16-opc.c

diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 83663adc838a1ba579fadfdcd0d54c4eb8576956..b955a6b629d949fe151d442d6d946072095e44bb 100644 (file)
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -1,5 +1,5 @@
 /* mips16-opc.c.  Mips16 opcode table.
-   Copyright (C) 1996-2017 Free Software Foundation, Inc.
+   Copyright (C) 1996-2020 Free Software Foundation, Inc.
    Contributed by Ian Lance Taylor, Cygnus Support
 
    This file is part of the GNU opcodes library.
@@ -62,7 +62,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
 
     case 'G': SPECIAL (0, 0, REG28);
     case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
-    case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
     case 'N': REG (5, 0, COPRO);
     case 'O': UINT (3, 21);
     case 'Q': REG (5, 16, HW);
@@ -82,6 +81,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
     case 'i': JALX (26, 0, 2);
     case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
     case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
+    case 'n': INT_BIAS (2, 0, 3, 1, 0, FALSE); /* (1 .. 4) */
+    case 'o': INT_ADJ (5, 16, 31, 4, FALSE);   /* (0 .. 31) << 4 */
     case 'r': MAPPED_REG (3, 16, GP, reg_m16_map);
     case 's': HINT (3, 24);
     case 'u': HINT (16, 0);
@@ -201,6 +202,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
 #define I32    INSN_ISA32
 #define I64    INSN_ISA64
 #define T3     INSN_3900
+#define IAMR2  INSN_INTERAPTIV_MR2
 
 #define E2     ASE_MIPS16E2
 #define E2MT   ASE_MIPS16E2_MT
@@ -442,7 +444,7 @@ const struct mips_opcode mips16_opcodes[] =
 {"xor",            "x,y",      0xe80e, 0xf81f,         MOD_1|RD_2,             SH,             I1,     0,      0 },
 {"xori",    "x,u",     0xf0006880, 0xf800f8e0, WR_1,                   0,              0,      E2,     0 },
   /* MIPS16e additions; see above for compact jumps.  */
-{"restore", "M",       0x6400, 0xff80,         WR_31|NODS,             MOD_SP,         I32,    0,      0 },
+{"restore", "m",       0x6400, 0xff80,         WR_31|NODS,             MOD_SP,         I32,    0,      0 },
 {"save",    "m",       0x6480, 0xff80,         NODS,                   RD_31|MOD_SP,   I32,    0,      0 },
 {"sdbbp",   "",                0xe801, 0xffff,         TRAP,                   SH,             I32,    0,      0 },
 {"sdbbp",   "6",       0xe801, 0xf81f,         TRAP,                   SH,             I32,    0,      0 },
@@ -465,6 +467,9 @@ const struct mips_opcode mips16_opcodes[] =
 {"evpe",    "",                0xf0276700, 0xffffffff, WR_C0,                  0,              0,      E2MT,   0 },
 {"evpe",    ".",       0xf0276700, 0xffffffff, WR_C0,                  0,              0,      E2MT,   0 },
 {"evpe",    "y",       0xf0236700, 0xffffff1f, WR_1|WR_C0,             0,              0,      E2MT,   0 },
+  /* interAptiv MR2 instruction extensions.  */
+{"copyw",   "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS,         0,              IAMR2,  0,      0 },
+{"ucopyw",  "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS,         0,              IAMR2,  0,      0 },
   /* Place asmacro at the bottom so that it catches any implementation
      specific macros that didn't match anything.  */
 {"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0,                  0,              I32,    0,      0 },