Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand.

[deliverable/binutils-gdb.git] / opcodes / or1k-ibld.c

diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c
index 6271f5c6d11ddcf00351abf15ccac8f2da4dbabc..d802a98462bf11a3836e0ce33074b74a9a716312 100644 (file)
--- a/opcodes/or1k-ibld.c
+++ b/opcodes/or1k-ibld.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
    - the resultant file is machine generated, cgen-ibld.in isn't
 
-   Copyright (C) 1996-2019 Free Software Foundation, Inc.
+   Copyright (C) 1996-2020 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
 
@@ -480,7 +480,10 @@ extract_normal (CGEN_CPU_DESC cd,
        abort ();
 
       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
-       return 0;
+       {
+         *valuep = 0;
+         return 0;
+       }
 
       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
     }
@@ -783,7 +786,7 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value);
-        value = ((((value) + (((DI) (pc) >> (13))))) << (13));
+        value = ((((value) + (((DI) (pc) >> (13))))) * (MAKEDI (0, 8192)));
         fields->f_disp21 = value;
       }
       break;
@@ -791,7 +794,7 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (MAKEDI (0, 4)))) + (pc));
         fields->f_disp26 = value;
       }
       break;