* elf64-x86-64.c (elf64_x86_64_elf_object_p): Make static.

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c8772d8015a8f0c69b16bb68bc45233d29f17406..311a5ba9f0fe4fa79ebc403ae1906b29befdb5dd 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -756,7 +756,7 @@ insert_mbe (insn, value, errmsg)
   /* me: location of last 1->0 transition */
   /* count: # transitions */
 
-  for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
+  for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
     {
       if ((uval & mask) && !last)
        {
@@ -2480,7 +2480,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtsrdin", X(31,114),        XRA_MASK,       PPC64,          { RS, RB } },
 
-{ "clf",     X(31,118), XRB_MASK,      POWER,          { RT, RA } },
+{ "clf",     X(31,118), XTO_MASK,      POWER,          { RA, RB } },
 
 { "lbzux",   X(31,119),        X_MASK,         COM,            { RT, RAL, RB } },
 
@@ -2907,25 +2907,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RT } },
 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,      { RT } },
-{ "mtummcr0",  XSPR(31,451,936),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc1",   XSPR(31,451,937),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc2",   XSPR(31,451,938),  XSPR_MASK, PPC750,   { RT } },
-{ "mtusia",    XSPR(31,451,939),  XSPR_MASK, PPC750,   { RT } },
-{ "mtummcr1",  XSPR(31,451,940),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc3",   XSPR(31,451,941),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc4",   XSPR(31,451,942),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr0",   XSPR(31,451,952),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc1",    XSPR(31,451,953),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc2",    XSPR(31,451,954),  XSPR_MASK, PPC750,   { RT } },
-{ "mtsia",     XSPR(31,451,955),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr1",   XSPR(31,451,956),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc3",    XSPR(31,451,957),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc4",    XSPR(31,451,958),  XSPR_MASK, PPC750,   { RT } },
-{ "mtl2cr",    XSPR(31,451,1017), XSPR_MASK, PPC750,   { RT } },
-{ "mtictc",    XSPR(31,451,1019), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm1",   XSPR(31,451,1020), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm2",   XSPR(31,451,1021), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm3",   XSPR(31,451,1022), XSPR_MASK, PPC750,   { RT } },
 { "mtdcr",   X(31,451),        X_MASK,         PPC403,         { SPR, RS } },
 
 { "divdu",   XO(31,457,0,0), XO_MASK,  PPC64,          { RT, RA, RB } },
@@ -3021,6 +3002,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,     { RT } },
 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,     { RT } },
 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,     { RT } },
+{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
+{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
+{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
+{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
+{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
+{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
+{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
+{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
+{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
+{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
+{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
+{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
+{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
+{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
+{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
+{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
+{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
+{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
 { "mtspr",   X(31,467),               X_MASK,       COM,       { SPR, RS } },
 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },