/* ppc-opc.c -- PowerPC opcode list
- Copyright (C) 1994-2019 Free Software Foundation, Inc.
+ Copyright (C) 1994-2020 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of the GNU opcodes library.
off a register, and implies that the next operand is a register in
parentheses. */
#define D34 DS + 1
- { 0x3ffffffff, PPC_OPSHIFT_INV, insert_d34, extract_d34,
+ { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The SI field in an 8-byte D form prefix instruction. */
#define SI34 D34 + 1
- { 0x3ffffffff, PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED },
+ { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED },
/* The NSI field in an 8-byte D form prefix instruction. This is the
same as the SI34 field, only negated. */
#define NSI34 SI34 + 1
- { 0x3ffffffff, PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
+ { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
/* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
/* A BD15 form instruction for extended conditional branch mnemonics. */
#define EBD15(op, aa, bo, lk) \
- (((op) & 0x3f) << 26) \
+ (((op) & 0x3fu) << 26) \
| (((aa) & 0xf) << 22) \
| (((bo) & 0x3) << 20) \
| ((lk) & 1)
/* A BD15 form instruction for extended conditional branch mnemonics
with BI. */
#define EBD15BI(op, aa, bo, bi, lk) \
- ((((op) & 0x3f) << 26) \
+ ((((op) & 0x3fu) << 26) \
| (((aa) & 0xf) << 22) \
| (((bo) & 0x3) << 20) \
| (((bi) & 0x3) << 16) \
{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
-{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
-
{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},