static long extract_nb PARAMS ((unsigned long, int *));
static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
static long extract_nsi PARAMS ((unsigned long, int *));
+static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
+static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
+static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
static long extract_rbs PARAMS ((unsigned long, int *));
static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
static long extract_sh6 PARAMS ((unsigned long, int *));
static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
static long extract_spr PARAMS ((unsigned long, int *));
+static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
+static long extract_tbr PARAMS ((unsigned long, int *));
\f
/* The operands table.
/* The zero index is used to indicate the end of the list of
operands. */
#define UNUSED (0)
- { 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0 },
/* The BA field in an XL form instruction. */
#define BA (UNUSED + 1)
#define BA_MASK (0x1f << 16)
- { 5, 16, 0, 0, 0, PPC_OPERAND_CR },
+ { 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */
#define BAT (BA + 1)
- { 5, 16, 0, insert_bat, extract_bat, PPC_OPERAND_FAKE },
+ { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
/* The BB field in an XL form instruction. */
#define BB (BAT + 1)
#define BB_MASK (0x1f << 11)
- { 5, 11, 0, 0, 0, PPC_OPERAND_CR },
+ { 5, 11, 0, 0, PPC_OPERAND_CR },
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
#define BBA (BB + 1)
- { 5, 11, 0, insert_bba, extract_bba, PPC_OPERAND_FAKE },
+ { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
/* The BD field in a B form instruction. The lower two bits are
forced to zero. */
#define BD (BBA + 1)
- { 16, 0, 1, insert_bd, extract_bd, PPC_OPERAND_RELATIVE },
+ { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when absolute addressing is
used. */
#define BDA (BD + 1)
- { 16, 0, 1, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE },
+ { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used.
This sets the y bit of the BO field appropriately. */
#define BDM (BDA + 1)
- { 16, 0, 1, insert_bdm, extract_bdm, PPC_OPERAND_RELATIVE },
+ { 16, 0, insert_bdm, extract_bdm,
+ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used
and absolute address is used. */
#define BDMA (BDM + 1)
- { 16, 0, 1, insert_bdm, extract_bdm, PPC_OPERAND_ABSOLUTE },
+ { 16, 0, insert_bdm, extract_bdm,
+ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used.
This sets the y bit of the BO field appropriately. */
#define BDP (BDMA + 1)
- { 16, 0, 1, insert_bdp, extract_bdp, PPC_OPERAND_RELATIVE },
+ { 16, 0, insert_bdp, extract_bdp,
+ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used
and absolute addressing is used. */
#define BDPA (BDP + 1)
- { 16, 0, 1, insert_bdp, extract_bdp, PPC_OPERAND_ABSOLUTE },
+ { 16, 0, insert_bdp, extract_bdp,
+ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BF field in an X or XL form instruction. */
#define BF (BDPA + 1)
- { 3, 23, 0, 0, 0, PPC_OPERAND_CR },
+ { 3, 23, 0, 0, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
#define OBF (BF + 1)
- { 3, 23, 0, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
#define BFA (OBF + 1)
- { 3, 18, 0, 0, 0, PPC_OPERAND_CR },
+ { 3, 18, 0, 0, PPC_OPERAND_CR },
/* The BI field in a B form or XL form instruction. */
#define BI (BFA + 1)
#define BI_MASK (0x1f << 16)
- { 5, 16, 0, 0, 0, PPC_OPERAND_CR },
+ { 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BO field in a B form instruction. Certain values are
illegal. */
#define BO (BI + 1)
#define BO_MASK (0x1f << 21)
- { 5, 21, 0, insert_bo, extract_bo, 0 },
+ { 5, 21, insert_bo, extract_bo, 0 },
/* The BO field in a B form instruction when the + or - modifier is
used. This is like the BO field, but it must be even. */
#define BOE (BO + 1)
- { 5, 21, 0, insert_boe, extract_boe, 0 },
+ { 5, 21, insert_boe, extract_boe, 0 },
/* The BT field in an X or XL form instruction. */
#define BT (BOE + 1)
- { 5, 21, 0, 0, 0, PPC_OPERAND_CR },
+ { 5, 21, 0, 0, PPC_OPERAND_CR },
/* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */
#define CR (BT + 1)
- { 5, 16, 0, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ { 5, 16, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
#define D (CR + 1)
- { 16, 0, 1, 0, 0, PPC_OPERAND_PARENS },
+ { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
#define DS (D + 1)
- { 16, 0, 1, insert_ds, extract_ds, PPC_OPERAND_PARENS },
+ { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The FL1 field in a POWER SC form instruction. */
#define FL1 (DS + 1)
- { 4, 12, 0, 0, 0, 0 },
+ { 4, 12, 0, 0, 0 },
/* The FL2 field in a POWER SC form instruction. */
#define FL2 (FL1 + 1)
- { 3, 2, 0, 0, 0, 0 },
+ { 3, 2, 0, 0, 0 },
/* The FLM field in an XFL form instruction. */
#define FLM (FL2 + 1)
- { 8, 17, 0, 0, 0, 0 },
+ { 8, 17, 0, 0, 0 },
/* The FRA field in an X or A form instruction. */
#define FRA (FLM + 1)
#define FRA_MASK (0x1f << 16)
- { 5, 16, 0, 0, 0, PPC_OPERAND_FPR },
+ { 5, 16, 0, 0, PPC_OPERAND_FPR },
/* The FRB field in an X or A form instruction. */
#define FRB (FRA + 1)
#define FRB_MASK (0x1f << 11)
- { 5, 11, 0, 0, 0, PPC_OPERAND_FPR },
+ { 5, 11, 0, 0, PPC_OPERAND_FPR },
/* The FRC field in an A form instruction. */
#define FRC (FRB + 1)
#define FRC_MASK (0x1f << 6)
- { 5, 6, 0, 0, 0, PPC_OPERAND_FPR },
+ { 5, 6, 0, 0, PPC_OPERAND_FPR },
/* The FRS field in an X form instruction or the FRT field in a D, X
or A form instruction. */
#define FRS (FRC + 1)
#define FRT (FRS)
- { 5, 21, 0, 0, 0, PPC_OPERAND_FPR },
+ { 5, 21, 0, 0, PPC_OPERAND_FPR },
/* The FXM field in an XFX instruction. */
#define FXM (FRS + 1)
- { 8, 12, 0, 0, 0, 0 },
+#define FXM_MASK (0xff << 12)
+ { 8, 12, 0, 0, 0 },
/* The L field in a D or X form instruction. */
#define L (FXM + 1)
- { 1, 21, 0, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SC form instruction. */
#define LEV (L + 1)
- { 7, 5, 0, 0, 0, 0 },
+ { 7, 5, 0, 0, 0 },
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
#define LI (LEV + 1)
- { 26, 0, 1, insert_li, extract_li, PPC_OPERAND_RELATIVE },
+ { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The LI field in an I form instruction when used as an absolute
address. */
#define LIA (LI + 1)
- { 26, 0, 1, insert_li, extract_li, PPC_OPERAND_ABSOLUTE },
+ { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The MB field in an M form instruction. */
#define MB (LIA + 1)
#define MB_MASK (0x1f << 6)
- { 5, 6, 0, 0, 0, 0 },
+ { 5, 6, 0, 0, 0 },
/* The ME field in an M form instruction. */
#define ME (MB + 1)
#define ME_MASK (0x1f << 1)
- { 5, 1, 0, 0, 0, 0 },
+ { 5, 1, 0, 0, 0 },
/* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */
#define MBE (ME + 1)
- { 5, 6, 0, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
- { 32, 0, 0, insert_mbe, extract_mbe, 0 },
+ { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
+ { 32, 0, insert_mbe, extract_mbe, 0 },
/* The MB or ME field in an MD or MDS form instruction. The high
bit is wrapped to the low end. */
#define MB6 (MBE + 2)
#define ME6 (MB6)
#define MB6_MASK (0x3f << 5)
- { 6, 5, 0, insert_mb6, extract_mb6, 0 },
+ { 6, 5, insert_mb6, extract_mb6, 0 },
/* The NB field in an X form instruction. The value 32 is stored as
0. */
#define NB (MB6 + 1)
- { 6, 11, 0, insert_nb, extract_nb, 0 },
+ { 6, 11, insert_nb, extract_nb, 0 },
/* The NSI field in a D form instruction. This is the same as the
SI field, only negated. */
#define NSI (NB + 1)
- { 16, 0, 1, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE },
+ { 16, 0, insert_nsi, extract_nsi,
+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
#define RA (NSI + 1)
#define RA_MASK (0x1f << 16)
- { 5, 16, 0, 0, 0, PPC_OPERAND_GPR },
+ { 5, 16, 0, 0, PPC_OPERAND_GPR },
+
+ /* The RA field in a D or X form instruction which is an updating
+ load, which means that the RA field may not be zero and may not
+ equal the RT field. */
+#define RAL (RA + 1)
+ { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
+
+ /* The RA field in an lmw instruction, which has special value
+ restrictions. */
+#define RAM (RAL + 1)
+ { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
+
+ /* The RA field in a D or X form instruction which is an updating
+ store or an updating floating point load, which means that the RA
+ field may not be zero. */
+#define RAS (RAM + 1)
+ { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
/* The RB field in an X, XO, M, or MDS form instruction. */
-#define RB (RA + 1)
+#define RB (RAS + 1)
#define RB_MASK (0x1f << 11)
- { 5, 11, 0, 0, 0, PPC_OPERAND_GPR },
+ { 5, 11, 0, 0, PPC_OPERAND_GPR },
/* The RB field in an X form instruction when it must be the same as
the RS field in the instruction. This is used for extended
mnemonics like mr. */
#define RBS (RB + 1)
- { 5, 1, 0, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
+ { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
instruction or the RT field in a D, DS, X, XFX or XO form
#define RS (RBS + 1)
#define RT (RS)
#define RT_MASK (0x1f << 21)
- { 5, 21, 0, 0, 0, PPC_OPERAND_GPR },
+ { 5, 21, 0, 0, PPC_OPERAND_GPR },
/* The SH field in an X or M form instruction. */
#define SH (RS + 1)
#define SH_MASK (0x1f << 11)
- { 5, 11, 0, 0, 0, 0 },
+ { 5, 11, 0, 0, 0 },
/* The SH field in an MD form instruction. This is split. */
#define SH6 (SH + 1)
#define SH6_MASK ((0x1f << 11) | (1 << 1))
- { 6, 1, 0, insert_sh6, extract_sh6, 0 },
+ { 6, 1, insert_sh6, extract_sh6, 0 },
/* The SI field in a D form instruction. */
#define SI (SH6 + 1)
- { 16, 0, 1, 0, 0, 0 },
+ { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
- /* The SPR or TBR field in an XFX form instruction. This is
- flipped--the lower 5 bits are stored in the upper 5 and vice-
- versa. */
-#define SPR (SI + 1)
-#define TBR (SPR)
+ /* The SI field in a D form instruction when we accept a wide range
+ of positive values. */
+#define SISIGNOPT (SI + 1)
+ { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The SPR field in an XFX form instruction. This is flipped--the
+ lower 5 bits are stored in the upper 5 and vice- versa. */
+#define SPR (SISIGNOPT + 1)
#define SPR_MASK (0x3ff << 11)
- { 10, 11, 0, insert_spr, extract_spr, 0 },
+ { 10, 11, insert_spr, extract_spr, 0 },
+
+ /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
+#define SPRBAT (SPR + 1)
+#define SPRBAT_MASK (0x3 << 17)
+ { 2, 17, 0, 0, 0 },
+
+ /* The SPRG register number in an XFX form m[ft]sprg instruction. */
+#define SPRG (SPRBAT + 1)
+#define SPRG_MASK (0x3 << 16)
+ { 2, 16, 0, 0, 0 },
/* The SR field in an X form instruction. */
-#define SR (SPR + 1)
- { 4, 16, 0, 0, 0, 0 },
+#define SR (SPRG + 1)
+ { 4, 16, 0, 0, 0 },
/* The SV field in a POWER SC form instruction. */
#define SV (SR + 1)
- { 14, 2, 0, 0, 0, 0 },
+ { 14, 2, 0, 0, 0 },
+
+ /* The TBR field in an XFX form instruction. This is like the SPR
+ field, but it is optional. */
+#define TBR (SV + 1)
+ { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
/* The TO field in a D or X form instruction. */
-#define TO (SV + 1)
+#define TO (TBR + 1)
#define TO_MASK (0x1f << 21)
- { 5, 21, 0, 0, 0, 0 },
+ { 5, 21, 0, 0, 0 },
/* The U field in an X form instruction. */
#define U (TO + 1)
- { 4, 12, 0, 0, 0, 0 },
+ { 4, 12, 0, 0, 0 },
/* The UI field in a D form instruction. */
#define UI (U + 1)
- { 16, 0, 0, 0, 0, 0 },
+ { 16, 0, 0, 0, 0 },
};
/* The functions used to insert and extract complicated operands. */
return - (insn & 0xffff);
}
+/* The RA field in a D or X form instruction which is an updating
+ load, which means that the RA field may not be zero and may not
+ equal the RT field. */
+
+static unsigned long
+insert_ral (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+{
+ if (value == 0
+ || value == ((insn >> 21) & 0x1f))
+ *errmsg = "invalid register operand when updating";
+ return insn | ((value & 0x1f) << 16);
+}
+
+/* The RA field in an lmw instruction, which has special value
+ restrictions. */
+
+static unsigned long
+insert_ram (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+{
+ if (value >= ((insn >> 21) & 0x1f))
+ *errmsg = "index register in load range";
+ return insn | ((value & 0x1f) << 16);
+}
+
+/* The RA field in a D or X form instruction which is an updating
+ store or an updating floating point load, which means that the RA
+ field may not be zero. */
+
+static unsigned long
+insert_ras (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+{
+ if (value == 0)
+ *errmsg = "invalid register operand when updating";
+ return insn | ((value & 0x1f) << 16);
+}
+
/* The RB field in an X form instruction when it must be the same as
the RS field in the instruction. This is used for extended
mnemonics like mr. This operand is marked FAKE. The insertion
return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
}
-/* The SPR or TBR field in an XFX form instruction. This is
- flipped--the lower 5 bits are stored in the upper 5 and vice-
- versa. */
+/* The SPR field in an XFX form instruction. This is flipped--the
+ lower 5 bits are stored in the upper 5 and vice- versa. */
static unsigned long
insert_spr (insn, value, errmsg)
{
return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
}
+
+/* The TBR field in an XFX instruction. This is just like SPR, but it
+ is optional. When TBR is omitted, it must be inserted as 268 (the
+ magic number of the TB register). These functions treat 0
+ (indicating an omitted optional operand) as 268. This means that
+ ``mftb 4,0'' is not handled correctly. This does not matter very
+ much, since the architecture manual does not define mftb as
+ accepting any values other than 268 or 269. */
+
+#define TB (268)
+
+static unsigned long
+insert_tbr (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+{
+ if (value == 0)
+ value = TB;
+ return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
+}
+
+static long
+extract_tbr (insn, invalid)
+ unsigned long insn;
+ int *invalid;
+{
+ long ret;
+
+ ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
+ if (ret == TB)
+ ret = 0;
+ return ret;
+}
\f
/* Macros used to form opcodes. */
#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
#define XS_MASK XS (0x3f, 0x1ff, 1)
+/* A mask for the FXM version of an XFX form instruction. */
+#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
+
+/* An XFX form instruction with the FXM field filled in. */
+#define XFXM(op, xop, fxm) \
+ (X ((op), (xop)) | (((fxm) & 0xff) << 12))
+
/* An XFX form instruction with the SPR field filled in. */
#define XSPR(op, xop, spr) \
(X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
#define XSPR_MASK (X_MASK | SPR_MASK)
+/* An XFX form instruction with the SPR field filled in except for the
+ SPRBAT field. */
+#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
+
+/* An XFX form instruction with the SPR field filled in except for the
+ SPRG field. */
+#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
fit on a single line. */
#define PPC PPC_OPCODE_PPC
#define POWER PPC_OPCODE_POWER
+#define POWER2 PPC_OPCODE_POWER2
#define B32 PPC_OPCODE_32
#define B64 PPC_OPCODE_64
+#define M601 PPC_OPCODE_601
\f
/* The opcode table.
{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
-{ "dozi", OP(9), OP_MASK, POWER, { RT, RA, SI } },
+{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
-{ "lis", OP(15), DRA_MASK, PPC, { RT, SI } },
-{ "liu", OP(15), DRA_MASK, POWER, { RT, UI } },
-{ "addis", OP(15), OP_MASK, PPC, { RT, RA, SI } },
-{ "cau", OP(15), OP_MASK, POWER, { RT, RA, UI } },
+{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
+{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
+{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
+{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
-{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
+{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
+{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
-{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
+{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
+{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
-{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
+{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
+{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
-{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
+{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
+{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
-{ "rlmi", M(22,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
-{ "rlmi.", M(22,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
+{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
+{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
-{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
+{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
-{ "maskg", XRC(31,29,0), X_MASK, POWER, { RA, RS, RB } },
-{ "maskg.", XRC(31,29,1), X_MASK, POWER, { RA, RS, RB } },
+{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
-{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
+{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
-{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RA, RB } },
+{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
-{ "lwzux", X(31,55), X_MASK, PPC, { RT, RA, RB } },
+{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
-{ "mul", XO(31,107,0,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "mul.", XO(31,107,0,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "mulo", XO(31,107,1,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "mulo.", XO(31,107,1,1), XO_MASK, POWER, { RT, RA, RB } },
+{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
-{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RA, RB } },
+{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "mtcrf", X(31,144), X_MASK|(1<<20)|(1<<11), PPC|POWER, { FXM, RS } },
+{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
+{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
-{ "slq", XRC(31,152,0), X_MASK, POWER, { RA, RS, RB } },
-{ "slq.", XRC(31,152,1), X_MASK, POWER, { RA, RS, RB } },
+{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "sle", XRC(31,153,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sle.", XRC(31,153,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RA, RB } },
+{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
-{ "stwux", X(31,183), X_MASK, PPC, { RS, RA, RB } },
+{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
-{ "sliq", XRC(31,184,0), X_MASK, POWER, { RA, RS, SH } },
-{ "sliq.", XRC(31,184,1), X_MASK, POWER, { RA, RS, SH } },
+{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
+{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
-{ "sllq", XRC(31,216,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sllq.", XRC(31,216,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "sleq", XRC(31,217,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sleq.", XRC(31,217,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
-{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RA, RB } },
+{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
-{ "slliq", XRC(31,248,0), X_MASK, POWER, { RA, RS, SH } },
-{ "slliq.", XRC(31,248,1), X_MASK, POWER, { RA, RS, SH } },
+{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
+{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
-{ "doz", XO(31,264,0,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "doz.", XO(31,264,0,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "dozo", XO(31,264,1,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "dozo.", XO(31,264,1,1), XO_MASK, POWER, { RT, RA, RB } },
+{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "lscbx", XRC(31,277,0), X_MASK, POWER, { RT, RA, RB } },
-{ "lscbx.", XRC(31,277,1), X_MASK, POWER, { RT, RA, RB } },
+{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
+{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
-{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RA, RB } },
+{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
-{ "div", XO(31,331,0,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "div.", XO(31,331,0,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "divo", XO(31,331,1,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "divo.", XO(31,331,1,1), XO_MASK, POWER, { RT, RA, RB } },
+{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
-{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER, { RT } },
+{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
+{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
+{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
+{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
+{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
+{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
+{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
+{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
+{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
+{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
+{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
+{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
+{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
-{ "abs", XO(31,360,0,0), XORB_MASK, POWER, { RT, RA } },
-{ "abs.", XO(31,360,0,1), XORB_MASK, POWER, { RT, RA } },
-{ "abso", XO(31,360,1,0), XORB_MASK, POWER, { RT, RA } },
-{ "abso.", XO(31,360,1,1), XORB_MASK, POWER, { RT, RA } },
+{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
+{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
+{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
+{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
-{ "divs", XO(31,363,0,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "divs.", XO(31,363,0,1), XO_MASK, POWER, { RT, RA, RB } },
-{ "divso", XO(31,363,1,0), XO_MASK, POWER, { RT, RA, RB } },
-{ "divso.", XO(31,363,1,1), XO_MASK, POWER, { RT, RA, RB } },
+{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
+{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
+{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
-{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RA, RB } },
+{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
-{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RA, RB } },
+{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
+{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
+
+{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
+
+{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
+
+{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
+
{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
-{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RA, RB } },
+{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER, { RS } },
+{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
+{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
+{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
+{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
+{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
+{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
+{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
+{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
+{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
+{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
+{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
+{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
+{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
-{ "nabs", XO(31,488,0,0), XORB_MASK, POWER, { RT, RA } },
-{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER, { RT, RA } },
-{ "nabso", XO(31,488,1,0), XORB_MASK, POWER, { RT, RA } },
-{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER, { RT, RA } },
+{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
+{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
+{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
+{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
-{ "clcs", X(31,531), XRB_MASK, POWER, { RT, RA } },
+{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
-{ "rrib", XRC(31,537,0), X_MASK, POWER, { RA, RS, RB } },
-{ "rrib.", XRC(31,537,1), X_MASK, POWER, { RA, RS, RB } },
+{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
-{ "maskir", XRC(31,541,0), X_MASK, POWER, { RA, RS, RB } },
-{ "maskir.", XRC(31,541,1), X_MASK, POWER, { RA, RS, RB } },
+{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
-{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RA, RB } },
+{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
-{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RA, RB } },
+{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
-{ "srq", XRC(31,664,0), X_MASK, POWER, { RA, RS, RB } },
-{ "srq.", XRC(31,664,1), X_MASK, POWER, { RA, RS, RB } },
+{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "sre", XRC(31,665,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sre.", XRC(31,665,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RA, RB } },
+{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
-{ "sriq", XRC(31,696,0), X_MASK, POWER, { RA, RS, SH } },
-{ "sriq.", XRC(31,696,1), X_MASK, POWER, { RA, RS, SH } },
+{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
+{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
-{ "srlq", XRC(31,728,0), X_MASK, POWER, { RA, RS, RB } },
-{ "srlq.", XRC(31,728,1), X_MASK, POWER, { RA, RS, RB } },
+{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "sreq", XRC(31,729,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sreq.", XRC(31,729,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RA, RB } },
+{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
-{ "srliq", XRC(31,760,0), X_MASK, POWER, { RA, RS, SH } },
-{ "srliq.", XRC(31,760,1), X_MASK, POWER, { RA, RS, SH } },
+{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
+{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
-{ "sraq", XRC(31,920,0), X_MASK, POWER, { RA, RS, RB } },
-{ "sraq.", XRC(31,920,1), X_MASK, POWER, { RA, RS, RB } },
+{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
-{ "srea", XRC(31,921,0), X_MASK, POWER, { RA, RS, RB } },
-{ "srea.", XRC(31,921,1), X_MASK, POWER, { RA, RS, RB } },
+{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
+{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
-{ "sraiq", XRC(31,952,0), X_MASK, POWER, { RA, RS, SH } },
-{ "sraiq.", XRC(31,952,1), X_MASK, POWER, { RA, RS, SH } },
+{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
+{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
-{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RA } },
+{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
-{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RA } },
+{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
-{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RA } },
+{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
-{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RA } },
+{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
-{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RA } },
+{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
-{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RA } },
+{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
-{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RA } },
+{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
-{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RA } },
+{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
-{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RA } },
+{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
-{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RA } },
+{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
-{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RA } },
+{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
-{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RA } },
+{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
+
+{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
+
+{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
-{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RA } },
+{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
+{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
+
+{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
+
{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
-{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RA } },
+{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
+{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
+{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
+{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
+{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
-{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
-{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
+{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
+{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
projects / deliverable / binutils-gdb.git / blobdiff