/* RISC-V disassembler
- Copyright (C) 2011-2017 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "libiberty.h"
#include "opcode/riscv.h"
#include "opintl.h"
#include "elf-bfd.h"
#include "elf/riscv.h"
-#include <stdint.h>
+#include "bfd_stdint.h"
#include <ctype.h>
struct riscv_private_data
}
else
{
- /* Invalid option. */
- fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
}
}
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
- pd->print_addr = pd->hi_addr[base_reg] + offset;
+ pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
pd->hi_addr[base_reg] = -1;
}
else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break;
+ case 'o':
case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break;
case 'b':
case 's':
+ if ((l & MASK_JALR) == MATCH_JALR)
+ maybe_print_address (pd, rs1, 0);
print (info->stream, "%s", riscv_gpr_names[rs1]);
break;
insnlen = riscv_insn_length (word);
+ /* RISC-V instructions are always little-endian. */
+ info->endian_code = BFD_ENDIAN_LITTLE;
+
info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
info->bytes_per_line = 8;
- info->display_endian = info->endian;
+ /* We don't support constant pools, so this must be code. */
+ info->display_endian = info->endian_code;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;
op = riscv_hash[OP_HASH_IDX (word)];
if (op != NULL)
{
- int xlen = 0;
+ unsigned xlen = 0;
/* If XLEN is not known, get its value from the ELF class. */
if (info->mach == bfd_mach_riscv64)
if (no_aliases && (op->pinfo & INSN_ALIAS))
continue;
/* Is this instruction restricted to a certain value of XLEN? */
- if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
+ if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
continue;
/* It's a match. */
pd->print_addr = -1;
}
+ /* Finish filling out insn_info fields. */
+ switch (op->pinfo & INSN_TYPE)
+ {
+ case INSN_BRANCH:
+ info->insn_type = dis_branch;
+ break;
+ case INSN_CONDBRANCH:
+ info->insn_type = dis_condbranch;
+ break;
+ case INSN_JSR:
+ info->insn_type = dis_jsr;
+ break;
+ case INSN_DREF:
+ info->insn_type = dis_dref;
+ break;
+ default:
+ break;
+ }
+
+ if (op->pinfo & INSN_DATA_SIZE)
+ {
+ int size = ((op->pinfo & INSN_DATA_SIZE)
+ >> INSN_DATA_SIZE_SHIFT);
+ info->data_size = 1 << (size - 1);
+ }
+
return insnlen;
}
}
return riscv_disassemble_insn (memaddr, insn, info);
}
+/* Prevent use of the fake labels that are generated as part of the DWARF
+ and for relaxable relocations in the assembler. */
+
+bfd_boolean
+riscv_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+ const char * name;
+
+ if (sym == NULL)
+ return FALSE;
+
+ name = bfd_asymbol_name (sym);
+
+ return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
+}
+
void
print_riscv_disassembler_options (FILE *stream)
{
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- numeric Print numeric reigster names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n\
no-aliases Disassemble only into canonical instructions, rather\n\