Make the assembler generate an error if there is an attempt to define a section with...

[deliverable/binutils-gdb.git] / opcodes / riscv-dis.c

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f1bbfdb1f14ce09a6095b79c85088fc4d9020d8d..47f9db02691d3afe1298678fcbdddafe9934499f 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1,5 +1,5 @@
 /* RISC-V disassembler
-   Copyright (C) 2011-2018 Free Software Foundation, Inc.
+   Copyright (C) 2011-2020 Free Software Foundation, Inc.
 
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
@@ -28,7 +28,7 @@
 #include "elf-bfd.h"
 #include "elf/riscv.h"
 
-#include <stdint.h>
+#include "bfd_stdint.h"
 #include <ctype.h>
 
 struct riscv_private_data
@@ -395,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
   insnlen = riscv_insn_length (word);
 
+  /* RISC-V instructions are always little-endian.  */
+  info->endian_code = BFD_ENDIAN_LITTLE;
+
   info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
   info->bytes_per_line = 8;
-  info->display_endian = info->endian;
+  /* We don't support constant pools, so this must be code.  */
+  info->display_endian = info->endian_code;
   info->insn_info_valid = 1;
   info->branch_delay_insns = 0;
   info->data_size = 0;