/* RISC-V disassembler
- Copyright (C) 2011-2019 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
unsigned int csr = EXTRACT_OPERAND (CSR, l);
switch (csr)
{
-#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}