/* RISC-V opcode list
- Copyright (C) 2011-2018 Free Software Foundation, Inc.
+ Copyright (C) 2011-2019 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
const struct riscv_opcode riscv_opcodes[] =
{
/* name, xlen, isa, operands, match, mask, match_func, pinfo. */
-{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
+{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
{"unimp", 0, {"I", 0}, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
{"ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
{"ebreak", 0, {"I", 0}, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
{"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
{"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
+{"beq", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
{"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
+{"bne", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
{"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
{"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
{"add", 0, {"I", 0}, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
applied to an add instruction, for relaxation to use. */
-{"add", 0, {"I", 0}, "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
+{"add", 0, {"I", 0}, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 },
{"add", 0, {"I", 0}, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
{"la", 0, {"I", 0}, "d,B", 0, (int) M_LA, match_never, INSN_MACRO },
{"lla", 0, {"I", 0}, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO },
{"fence", 0, {"I", 0}, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, {"I", 0}, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, {"I", 0}, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"fence.tso", 0, {"I", 0}, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
{"rdcycle", 0, {"I", 0}, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, {"I", 0}, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
{"rdtime", 0, {"I", 0}, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
{"fcvt.q.lu", 64, {"Q", 0}, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
/* Compressed instructions. */
+{"c.unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
{"c.ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
{"c.jr", 0, {"C", 0}, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH },
{"c.jalr", 0, {"C", 0}, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR },
{"ci", 0, {"C", 0}, "O2,CF3,d,Co", 0, 0, match_opcode, 0 },
{"ci", 0, {"C", 0}, "O2,CF3,D,Co", 0, 0, match_opcode, 0 },
-{"ciw", 0, {"C", 0}, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
-{"ciw", 0, {"C", 0}, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
+{"ciw", 0, {"C", 0}, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
+{"ciw", 0, {"C", 0}, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
+
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, 0 },
{"cb", 0, {"C", 0}, "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 },
{"cb", 0, {"C", 0}, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },