[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.

[deliverable/binutils-gdb.git] / opcodes / rl78-decode.opc

diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc
index 8bb8d0940dbf5b33f44a9053ebef8600b089a618..89d89fe72e66a77c946a79695563869931d89594 100644 (file)
--- a/opcodes/rl78-decode.opc
+++ b/opcodes/rl78-decode.opc
@@ -614,10 +614,10 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1001 1001                  mov     %e0, %1                         */
   ID(mov); DM(DE, 0); SR(A);
 
-/** 1100 1010                  mov     %e0, #%1                        */
+/** 1100 1010                  mov     %ea0, #%1                       */
   ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
 
-/** 1001 1010                  mov     %e0, %1                         */
+/** 1001 1010                  mov     %ea0, %1                                */
   ID(mov); DM(DE, IMMU(1)); SR(A);
 
 /** 1001 1011                  mov     %e0, %1                         */
@@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1000 1001                  mov     %0, %e1                         */
   ID(mov); DR(A); SM(DE, 0);
 
-/** 1000 1010                  mov     %0, %e1                         */
+/** 1000 1010                  mov     %0, %ea1                        */
   ID(mov); DR(A); SM(DE, IMMU(1));
 
 /** 1000 1011                  mov     %0, %e1                         */
@@ -776,7 +776,7 @@ rl78_decode_opcode (unsigned long pc AU,
        break;
       }
 
-/** 1001 1110                  mov     %0, %1                          */
+/** 1001 1110                  mov     %s0, %1                         */
   ID(mov); DM(None, SFR); SR(A);
 
 /*----------------------------------------------------------------------*/
@@ -818,7 +818,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1011 1001                  movw    %e0, %1                         */
   ID(mov); W(); DM(DE, 0); SR(AX);
 
-/** 1011 1010                  movw    %e0, %1                         */
+/** 1011 1010                  movw    %ea0, %1                                */
   ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
 
 /** 1011 1011                  movw    %e0, %1                         */
@@ -837,7 +837,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1010 1001                  movw    %0, %e1                         */
   ID(mov); W(); DR(AX); SM(DE, 0);
 
-/** 1010 1010                  movw    %0, %e1                         */
+/** 1010 1010                  movw    %0, %ea1                                */
   ID(mov); W(); DR(AX); SM(DE, IMMU(1));
 
 /** 1010 1011                  movw    %0, %e1                         */
@@ -894,17 +894,16 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1011 1101                  movw    %0, %1                          */
   ID(mov); W(); DM(None, SADDR); SR(AX);
 
-/** 1100 1011                  movw    %0, #%1                         */
+/** 1100 1011                  movw    %s0, #%1                        */
   ID(mov); W(); DM(None, SFR); SC(IMMU(2));
 
-/** 1011 1110                  movw    %0, %1                          */
+/** 1011 1110                  movw    %s0, %1                         */
   ID(mov); W(); DM(None, SFR); SR(AX);
 
 /*----------------------------------------------------------------------*/
 
 /** 1101 0110                  mulu    x                               */
-  if (isa == RL78_ISA_G14)
-    ID(mulu);
+  ID(mulu);
 
 /*----------------------------------------------------------------------*/
 
@@ -1206,7 +1205,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 0110 0001 1010 1110                xch     %0, %e1                         */
   ID(xch); DR(A); SM(DE, 0);
 
-/** 0110 0001 1010 1111                xch     %0, %e1                         */
+/** 0110 0001 1010 1111                xch     %0, %ea1                                */
   ID(xch); DR(A); SM(DE, IMMU(1));
 
 /** 0110 0001 1010 1100                xch     %0, %e1                         */
@@ -1228,7 +1227,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 0110 0001 1010 1000                xch     %0, %1                          */
   ID(xch); DR(A); SM(None, SADDR);
 
-/** 0110 0001 1010 1011                xch     %0, %1                          */
+/** 0110 0001 1010 1011                xch     %0, %s1                         */
   ID(xch); DR(A); SM(None, SFR);
 
 /** 0000 1000                  xch     a, x                            */