/* Print SPARC instructions.
- Copyright (C) 1989-2017 Free Software Foundation, Inc.
+ Copyright (C) 1989-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
| (1 << SPARC_OPCODE_ARCH_V9D) \
| (1 << SPARC_OPCODE_ARCH_V9E) \
| (1 << SPARC_OPCODE_ARCH_V9V) \
- | (1 << SPARC_OPCODE_ARCH_V9M))
+ | (1 << SPARC_OPCODE_ARCH_V9M) \
+ | (1 << SPARC_OPCODE_ARCH_M8))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
/* Sign-extend a value which is N bits long. */
#define SEX(value, bits) \
- ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
- >> ((8 * sizeof (int)) - bits) )
+ ((int) (((value & ((1u << (bits - 1) << 1) - 1)) \
+ ^ (1u << (bits - 1))) - (1u << (bits - 1))))
static char *reg_names[] =
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
#define X_IMM22(i) X_DISP22 (i)
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+#define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1))
/* These are for v9. */
#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
case bfd_mach_sparc_v8plusm :
case bfd_mach_sparc_v9m :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
+ case bfd_mach_sparc_v8plusm8 :
+ case bfd_mach_sparc_v9m8 :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8);
}
abort ();
}
wrong with the opcode table. */
if (match0 & lose0)
{
- fprintf
- (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op0->name, match0, lose0);
op0->lose &= ~op0->match;
lose0 = op0->lose;
if (match1 & lose1)
{
- fprintf
- (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op1->name, match1, lose1);
op1->lose &= ~op1->match;
lose1 = op1->lose;
another, it is important to order the opcodes in the right order. */
for (i = 0; i < 32; ++i)
{
- unsigned long int x = 1 << i;
+ unsigned long int x = 1ul << i;
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
for (i = 0; i < 32; ++i)
{
- unsigned long int x = 1 << i;
+ unsigned long int x = 1ul << i;
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
return i;
}
else
- fprintf (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
- op0->name, op1->name);
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
+ op0->name, op1->name);
}
/* Fewer arguments are preferred. */
break;
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
+ case ';': /* Double/even multiple of 8 doubles. */
fregx (X_RS1 (insn));
break;
break;
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
+ case ':': /* Double/even multiple of 8 doubles. */
fregx (X_RS2 (insn));
break;
case '}': /* Double/even. */
fregx (X_RD (insn));
break;
+
+ case '^': /* Double/even multiple of 8 doubles. */
+ fregx (X_RD (insn) & ~0x6);
+ break;
+
+ case '\'': /* Double/even in FPCMPSHL. */
+ fregx (X_RS2 (insn | 0x11));
+ break;
+
#undef freg
#undef fregx
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
- ((unsigned) 0xFFFFFFFF
- & ((int) X_IMM22 (insn) << 10)));
+ (unsigned) X_IMM22 (insn) << 10);
break;
case 'i': /* 13 bit immediate. */
(*info->fprintf_func) (stream, "%%mcdper");
break;
+ case '&':
+ (*info->fprintf_func) (stream, "%%entropy");
+ break;
+
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
+ X_ASI (insn)));
break;
+ case '|': /* 2-bit immediate */
+ (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn));
+ break;
+
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
- info->target =
- ((unsigned) 0xFFFFFFFF
- & ((int) X_IMM22 (prev_insn) << 10));
+ info->target = (unsigned) X_IMM22 (prev_insn) << 10;
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else