Add multi-target tests

[deliverable/binutils-gdb.git] / opcodes / sparc-opc.c

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 6de9305d1450bdf0e1661ed36bdc3bb4584c6b55..870676035831a3290bb9cf83228ce03a6eddcec7 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1,5 +1,5 @@
 /* Table of opcodes for the sparc.
-   Copyright (C) 1989-2018 Free Software Foundation, Inc.
+   Copyright (C) 1989-2020 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -71,6 +71,7 @@
                          | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
                          | MASK_M8)
 #define sparclet       (MASK_SPARCLET)
+#define leon           (MASK_LEON)
 /* sparclet insns supported by leon.  */
 #define letandleon     (MASK_SPARCLET | MASK_LEON)
 #define sparclite      (MASK_SPARCLITE)
@@ -1023,6 +1024,13 @@ wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr  */
 wrasr (27, HWCAP_PAUSE, 0, v9e),  /* wr ...,%pause  */
 wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait  */
 
+{ "pwr",       F3(2, 0x31, 0)|RD(1),   F3(~2, ~0x31, ~0)|RD(~1)|ASI(~0),               "1,2,p", 0, 0, 0, leon }, /* pwr r,r,%psr */
+{ "pwr",       F3(2, 0x31, 1)|RD(1),   F3(~2, ~0x31, ~1)|RD(~1),                       "1,i,p", 0, 0, 0, leon }, /* pwr r,i,%psr */
+{ "pwr",       F3(2, 0x31, 0)|RD(1),   F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|ASI(~0),        "2,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,rs2,%psr */
+{ "pwr",       F3(2, 0x31, 1)|RD(1),   F3(~2, ~0x31, ~1)|RD(~1)|RS1_G0,                "i,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,i,%psr */
+{ "pwr",       F3(2, 0x31, 1)|RD(1),   F3(~2, ~0x31, ~1)|RD(~1)|SIMM13(~0),            "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,0,%psr */
+{ "pwr",       F3(2, 0x31, 0)|RD(1),   F3(~2, ~0x31, ~0)|RD(~1)|ASI_RS2(~0),           "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,%g0,%psr */
+
 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */
 
 { "rd",        F3(2, 0x28, 0)|RS1(2),          F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),   "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */