/* Table of opcodes for the Texas Instruments TMS320C54X
- Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1999-2019 Free Software Foundation, Inc.
Contributed by Timothy Wall (twall@cygnus.com)
- This program is free software; you can redistribute it and/or modify
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/tic54x.h"
/* these are the only register names not found in mmregs */
-const symbol regs[] = {
+const tic54x_symbol regs[] = {
{ "AR0", 16 }, { "ar0", 16 },
{ "AR1", 17 }, { "ar1", 17 },
{ "AR2", 18 }, { "ar2", 18 },
/* status bits, MM registers, condition codes, etc */
/* some symbols are only valid for certain chips... */
-const symbol mmregs[] = {
+const tic54x_symbol mmregs[] = {
{ "IMR", 0 }, { "imr", 0 },
{ "IFR", 1 }, { "ifr", 1 },
{ "ST0", 6 }, { "st0", 6 },
{ NULL, 0},
};
-const symbol condition_codes[] = {
+const tic54x_symbol condition_codes[] = {
/* condition codes */
{ "UNC", 0 }, { "unc", 0 },
#define CC1 0x40
{ NULL, 0 }
};
-const symbol cc2_codes[] = {
+const tic54x_symbol cc2_codes[] = {
{ "UNC", 0 }, { "unc", 0 },
{ "AEQ", 5 }, { "aeq", 5 },
{ "ANEQ", 4 }, { "aneq", 4 },
{ NULL, 0 },
};
-const symbol cc3_codes[] = {
+const tic54x_symbol cc3_codes[] = {
{ "EQ", 0x0000 }, { "eq", 0x0000 },
{ "LT", 0x0100 }, { "lt", 0x0100 },
{ "GT", 0x0200 }, { "gt", 0x0200 },
};
/* FIXME -- also allow decimal digits */
-const symbol status_bits[] = {
+const tic54x_symbol status_bits[] = {
/* status register 0 */
{ "TC", 12 }, { "tc", 12 },
{ "C", 11 }, { "c", 11 },
#define ZPAR 0,{OP_None}
#define REST 0,0,ZPAR
#define XREST ZPAR
-const template tic54x_unknown_opcode =
+const insn_template tic54x_unknown_opcode =
{ "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
-const template tic54x_optab[] = {
+const insn_template tic54x_optab[] = {
/* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
{ "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
{ "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
};
/* assume all parallel instructions have at least three operands */
-const template tic54x_paroptab[] = {
+const insn_template tic54x_paroptab[] = {
{ "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
"mac", {OP_Ymem,OPT|OP_RND},},
{ "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,