Revert spurious unrelated changes from last commit. Oops.

[deliverable/binutils-gdb.git] / opcodes / tic80-opc.c

diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c
index 061b63761c4d13ac6c5d9349d98342f94c93ea87..4cdd06a64ff6163112d27b46affaad28f5fa557b 100644 (file)
--- a/opcodes/tic80-opc.c
+++ b/opcodes/tic80-opc.c
@@ -1,5 +1,5 @@
 /* Opcode table for TI TMS320C80 (MVP).
-   Copyright 1996 Free Software Foundation, Inc.
+   Copyright 1996, 1999 Free Software Foundation, Inc.
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -15,10 +15,11 @@ the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
 
 #include <stdio.h>
-#include "ansidecl.h"
+#include "sysdep.h"
 #include "opcode/tic80.h"
 
 /* This file holds various tables for the TMS320C80 (MVP).
@@ -604,11 +605,11 @@ const struct tic80_opcode tic80_opcodes[] = {
   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
      this specific bit pattern will get disassembled as a br rather than bbz. */
 
-  {"br",       OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br",       OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}     },
+  {"br",       OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br",       OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}         },
-  {"br.a",     OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br.a",     OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}     },
+  {"br.a",     OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br.a",     OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}         },
 
   /* Signed integer ADD */
@@ -652,38 +653,38 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Branch Bit One - nonannulled */
 
-  {"bbo",      OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo",      OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
+  {"bbo",      OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo",      OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit One - annulled */
 
-  {"bbo.a",    OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo.a",    OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
+  {"bbo.a",    OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo.a",    OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - nonannulled */
 
-  {"bbz",      OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz",      OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
+  {"bbz",      OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz",      OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - annulled */
 
-  {"bbz.a",    OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz.a",    OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
+  {"bbz.a",    OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz.a",    OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Conditional - nonannulled */
 
-  {"bcnd",     OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd",     OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
+  {"bcnd",     OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd",     OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Conditional - annulled */
 
-  {"bcnd.a",   OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd.a",   OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
+  {"bcnd.a",   OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd.a",   OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Control Register */
@@ -694,14 +695,14 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Branch and save return - nonannulled */
 
-  {"bsr",      OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr",      OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
+  {"bsr",      OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr",      OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Branch and save return - annulled */
 
-  {"bsr.a",    OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr.a",    OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
+  {"bsr.a",    OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr.a",    OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Send command */