sim/aarch64: Fix register ordering bug in blr (PR sim/25318)

[deliverable/binutils-gdb.git] / sim / aarch64 / ChangeLog

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+2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
+
+       PR sim/25318
+       * simulator.c (blr): Read destination register before calling
+       aarch64_save_LR.
+
 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 
        * cpustate.c: Add 'libiberty.h' include.