+2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * cpustate.c: Add 'libiberty.h' include.
+ * interp.c: Add 'sim-assert.h' include.
+
+2017-09-06 John Baldwin <jhb@FreeBSD.org>
+
+ * configure: Regenerate.
+
+2017-04-22 Jim Wilson <jim.wilson@linaro.org>
+
+ * simulator.c (vec_load): Add M argument. Rewrite to iterate over
+ registers based on structure size.
+ (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
+ (LD1_1): Replace with call to vec_load.
+ (vec_store): Add new M argument. Rewrite to iterate over registers
+ based on structure size.
+ (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
+ (ST1_1): Replace with call to vec_store.
+
+2017-04-08 Jim Wilson <jim.wilson@linaro.org>
+
+ * simulator.c (do_vec_FCVTL): New.
+ (do_vec_op1): Call do_vec_FCVTL.
+
+ * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
+ do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
+ (do_scalar_vec): Add calls to new functions.
+
+2017-03-25 Jim Wilson <jim.wilson@linaro.org>
+
+ * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
+ flag check.
+
+2017-03-03 Jim Wilson <jim.wilson@linaro.org>
+
+ * simulator.c (mul64hi): Shift carry left by 32.
+ (smulh): Change signum to negate. If negate, invert result, and add
+ carry bit if low part of multiply result is zero.
+
2017-02-25 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (do_vec_SMOV_into_scalar): New.