sim/aarch64: Fix register ordering bug in blr (PR sim/25318)

[deliverable/binutils-gdb.git] / sim / aarch64 / simulator.c

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 84919d6b1fcd3c64e3cf031bd5b4c439018f1f68..5f16a69478c8cb0edab4f85274c489cec0b23ad2 100644 (file)
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -13437,13 +13437,12 @@ br (sim_cpu *cpu)
 static void
 blr (sim_cpu *cpu)
 {
-  unsigned rn = INSTR (9, 5);
+  /* Ensure we read the destination before we write LR.  */
+  uint64_t target = aarch64_get_reg_u64 (cpu, INSTR (9, 5), NO_SP);
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
-  /* The pseudo code in the spec says we update LR before fetching.
-     the value from the rn.  */
   aarch64_save_LR (cpu);
-  aarch64_set_next_PC (cpu, aarch64_get_reg_u64 (cpu, rn, NO_SP));
+  aarch64_set_next_PC (cpu, target);
 
   if (TRACE_BRANCH_P (cpu))
     {