Automatic date update in version.in

[deliverable/binutils-gdb.git] / sim / arm / arminit.c

diff --git a/sim/arm/arminit.c b/sim/arm/arminit.c
index 2f6e73df3ca35406ddb973b6174cd0bce97c5eba..bc5456f47b77ba91210438939ddf42cf509ea8f1 100644 (file)
--- a/sim/arm/arminit.c
+++ b/sim/arm/arminit.c
@@ -1,22 +1,27 @@
 /*  arminit.c -- ARMulator initialization:  ARM6 Instruction Emulator.
     Copyright (C) 1994 Advanced RISC Machines Ltd.
- 
+
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
+    the Free Software Foundation; either version 3 of the License, or
     (at your option) any later version.
- 
+
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU General Public License for more details.
- 
+
     You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+    along with this program; if not, see <http://www.gnu.org/licenses/>. */
+
+/* This must come before any other includes.  */
+#include "defs.h"
+
+#include <string.h>
 
 #include "armdefs.h"
 #include "armemu.h"
+#include "dbg_rdi.h"
 
 /***************************************************************************\
 *                 Definitions for the emulator architecture                 *
@@ -38,6 +43,10 @@ unsigned ARMul_MultTable[32] =
 ARMword ARMul_ImmedTable[4096];        /* immediate DP LHS values */
 char ARMul_BitList[256];       /* number of bits in a byte table */
 
+/* The PC pipeline value depends on whether ARM
+   or Thumb instructions are being executed.  */
+ARMword isize;
+
 /***************************************************************************\
 *         Call this routine once to set up the emulator's tables.           *
 \***************************************************************************/
@@ -106,6 +115,9 @@ ARMul_NewState (void)
   state->OSptr = NULL;
   state->CommandLine = NULL;
 
+  state->CP14R0_CCD = -1;
+  state->LastTime = 0;
+
   state->EventSet = 0;
   state->Now = 0;
   state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
@@ -124,6 +136,8 @@ ARMul_NewState (void)
   state->is_v5 = LOW;
   state->is_v5e = LOW;
   state->is_XScale = LOW;
+  state->is_iWMMXt = LOW;
+  state->is_v6 = LOW;
 
   ARMul_Reset (state);
 
@@ -154,6 +168,13 @@ ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
   state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
   state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
   state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
+  state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
+  state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
+  state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
+
+  /* Only initialse the coprocessor support once we
+     know what kind of chip we are dealing with.  */
+  ARMul_CoProInit (state);
 }
 
 /***************************************************************************\
@@ -184,7 +205,6 @@ ARMul_Reset (ARMul_State * state)
   FLUSHPIPE;
 
   state->EndCondition = 0;
-  state->ErrorCode = 0;
 
   state->Exception = FALSE;
   state->NresetSig = HIGH;
@@ -266,9 +286,6 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
 
   state->Aborted = FALSE;
 
-  if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
-    return;
-
   if (state->prog32Sig)
     if (ARMul_MODE26BIT)
       temp = R15PC;
@@ -299,14 +316,40 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
       SETABORT (IBIT, SVC26MODE, isize);
       break;
     case ARMul_IRQV:           /* IRQ */
-      SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
+      if (   ! state->is_XScale
+         || ! state->CPRead[13] (state, 0, & temp)
+         || (temp & ARMul_CP13_R0_IRQ))
+        SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
       break;
     case ARMul_FIQV:           /* FIQ */
-      SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
+      if (   ! state->is_XScale
+         || ! state->CPRead[13] (state, 0, & temp)
+         || (temp & ARMul_CP13_R0_FIQ))
+        SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
       break;
     }
   if (ARMul_MODE32BIT)
     ARMul_SetR15 (state, vector);
   else
     ARMul_SetR15 (state, R15CCINTMODE | vector);
+
+  if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0)
+    {
+      /* No vector has been installed.  Rather than simulating whatever
+        random bits might happen to be at address 0x20 onwards we elect
+        to stop.  */
+      switch (vector)
+       {
+       case ARMul_ResetV: state->EndCondition = RDIError_Reset; break;
+       case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break;
+       case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break;
+       case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break;
+       case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break;
+       case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break;
+       case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break;
+       case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break;
+       default: break;
+       }
+      state->Emulate = FALSE;
+    }
 }