Add iWMMXt support to ARM simulator

[deliverable/binutils-gdb.git] / sim / arm / wrapper.c

diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index f13d32928b06585db22c7df394ddbb6539b1354f..46410c3f877092a90f4708d3f0c858556e5e46aa 100644 (file)
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -263,10 +263,34 @@ sim_create_inferior (sd, abfd, argv, env)
       /* We wouldn't set the machine type with earlier toolchains, so we
         explicitly select a processor capable of supporting all ARMs in
         32bit mode.  */
+      /* We choose the XScale rather than the iWMMXt, because the iWMMXt
+        removes the FPE emulator, since it conflicts with its coprocessors.
+        For the most generic ARM support, we want the FPE emulator in place.  */
     case bfd_mach_arm_XScale:
       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
       break;
 
+    case bfd_mach_arm_iWMMXt:
+      {
+       extern int SWI_vector_installed;
+       ARMword i;
+
+       if (! SWI_vector_installed)
+         {
+           /* Intialise the hardware vectors to zero.  */
+           if (! SWI_vector_installed)
+             for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
+               ARMul_WriteWord (state, i, 0);
+
+           /* ARM_WriteWord will have detected the write to the SWI vector,
+              but we want SWI_vector_installed to remain at 0 so that thumb
+              mode breakpoints will work.  */
+           SWI_vector_installed = 0;
+         }
+      }
+      ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
+      break;
+
     case bfd_mach_arm_ep9312:
       ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
       break;
@@ -481,6 +505,41 @@ sim_store_register (sd, rn, memory, length)
       memcpy (&DSPsc, memory, sizeof DSPsc);
       return sizeof DSPsc;
 
+#ifdef __IWMMXT__
+    case SIM_ARM_IWMMXT_COP0R0_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R1_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R2_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R3_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R4_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R5_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R6_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R7_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R8_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R9_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R10_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R11_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R12_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R13_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R14_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R15_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R0_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R1_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R2_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R3_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R4_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R5_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R6_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R7_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R8_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R9_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R10_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R11_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R12_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R13_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R14_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R15_REGNUM:
+      return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
+#endif
     default:
       return 0;
     }
@@ -560,6 +619,41 @@ sim_fetch_register (sd, rn, memory, length)
       memcpy (memory, & DSPsc, sizeof DSPsc);
       return sizeof DSPsc;
 
+#ifdef __IWMMXT__
+    case SIM_ARM_IWMMXT_COP0R0_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R1_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R2_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R3_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R4_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R5_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R6_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R7_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R8_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R9_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R10_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R11_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R12_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R13_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R14_REGNUM:
+    case SIM_ARM_IWMMXT_COP0R15_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R0_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R1_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R2_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R3_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R4_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R5_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R6_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R7_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R8_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R9_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R10_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R11_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R12_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R13_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R14_REGNUM:
+    case SIM_ARM_IWMMXT_COP1R15_REGNUM:
+      return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
+#endif
     default:
       return 0;
     }
@@ -822,6 +916,9 @@ sim_stop_reason (sd, reason, sigrc)
       *reason = sim_stopped;
       if (state->EndCondition == RDIError_BreakpointReached)
        *sigrc = SIGTRAP;
+      else if (   state->EndCondition == RDIError_DataAbort
+              || state->EndCondition == RDIError_AddressException)
+       *sigrc = SIGBUS;
       else
        *sigrc = 0;
     }