ubsan: aarch64: left shift cannot be represented in type 'int64_t'

[deliverable/binutils-gdb.git] / sim / bfin / bfin-sim.c

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 90e09106c5b32c21dbc9a799e96bf18419febad6..c7214c38da1dd66f92ec00a9fbc9c9869d39b578 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -1,6 +1,6 @@
 /* Simulator for Analog Devices Blackfin processors.
 
-   Copyright (C) 2005-2013 Free Software Foundation, Inc.
+   Copyright (C) 2005-2019 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -1741,7 +1741,7 @@ hwloop_get_next_pc (SIM_CPU *cpu, bu32 pc, bu32 insn_len)
   for (i = 1; i >= 0; --i)
     if (LCREG (i) > 1 && pc == LBREG (i))
       {
-       TRACE_BRANCH (cpu, pc, LTREG (i), i, "Hardware loop %i", i);
+       BFIN_TRACE_BRANCH (cpu, pc, LTREG (i), i, "Hardware loop %i", i);
        return LTREG (i);
       }
 
@@ -1773,7 +1773,7 @@ decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
       IFETCH_CHECK (newpc);
       if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
        illegal_instruction_combination (cpu);
-      TRACE_BRANCH (cpu, pc, newpc, -1, "RTS");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "RTS");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       CYCLE_DELAY = 5;
@@ -1893,7 +1893,7 @@ decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
       IFETCH_CHECK (newpc);
       if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
        illegal_instruction_combination (cpu);
-      TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (Preg)");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (Preg)");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
@@ -1907,7 +1907,7 @@ decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
       IFETCH_CHECK (newpc);
       if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
        illegal_instruction_combination (cpu);
-      TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (Preg)");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (Preg)");
       /* If we're at the end of a hardware loop, RETS is going to be
          the top of the loop rather than the next instruction.  */
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2));
@@ -1924,7 +1924,7 @@ decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
       IFETCH_CHECK (newpc);
       if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
        illegal_instruction_combination (cpu);
-      TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (PC + Preg)");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (PC + Preg)");
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2));
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
@@ -1939,7 +1939,7 @@ decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
       IFETCH_CHECK (newpc);
       if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
        illegal_instruction_combination (cpu);
-      TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (PC + Preg)");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (PC + Preg)");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
@@ -2444,7 +2444,7 @@ decode_BRCC_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
   if (cond)
     {
       bu32 newpc = pc + pcrel;
-      TRACE_BRANCH (cpu, pc, newpc, -1, "Conditional JUMP");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "Conditional JUMP");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
@@ -2477,7 +2477,7 @@ decode_UJUMP_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc)
   if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
-  TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.S");
+  BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.S");
 
   SET_PCREG (newpc);
   BFIN_CPU_STATE.did_jump = true;
@@ -3292,7 +3292,7 @@ decode_LDST_0 (SIM_CPU *cpu, bu16 iw0)
   int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
   int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
   int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
-  const char * const posts[] = { "++", "--", "" };
+  const char * const posts[] = { "++", "--", "", "<INV>" };
   const char *post = posts[aop];
   const char *ptr_name = get_preg_name (ptr);
 
@@ -3619,11 +3619,11 @@ decode_CALLa_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc)
 
   if (S == 1)
     {
-      TRACE_BRANCH (cpu, pc, newpc, -1, "CALL");
+      BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "CALL");
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 4));
     }
   else
-    TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.L");
+    BFIN_TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.L");
 
   SET_PCREG (newpc);
   BFIN_CPU_STATE.did_jump = true;
@@ -4318,7 +4318,7 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       SET_AREG (1, 0);
     }
   else if ((aop == 0 || aop == 1 || aop == 2) && s == 1 && aopcde == 8
-          && x == 0 && s == 1 && HL == 0)
+          && x == 0 && HL == 0)
     {
       bs40 acc0 = get_extended_acc (cpu, 0);
       bs40 acc1 = get_extended_acc (cpu, 1);
@@ -4537,7 +4537,7 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
   else if ((aop == 0 || aop == 1) && aopcde == 14 && x == 0 && s == 0)
     {
       bs40 src_acc = get_extended_acc (cpu, aop);
-      int v = 0;
+      bu32 v = 0;
 
       TRACE_INSN (cpu, "A%i = - A%i;", HL, aop);
 
@@ -5148,6 +5148,19 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       TRACE_INSN (cpu, "(R%i, R%i) = SEARCH R%i (%s);",
                  dst1, dst0, src0, searchmodes[aop]);
 
+      /* XXX: The parallel version is a bit weird in its limits:
+
+         This instruction can be issued in parallel with the combination of one
+         16-bit length load instruction to the P0 register and one 16-bit NOP.
+         No other instructions can be issued in parallel with the Vector Search
+         instruction. Note the following legal and illegal forms.
+         (r1, r0) = search r2 (LT) || r2 = [p0++p3]; // ILLEGAL
+         (r1, r0) = search r2 (LT) || r2 = [p0++];   // LEGAL
+         (r1, r0) = search r2 (LT) || r2 = [p0++];   // LEGAL
+
+         Unfortunately, our parallel insn state doesn't (currently) track enough
+         details to be able to check this.  */
+
       if (dst0 == dst1)
        illegal_instruction_combination (cpu);
 
@@ -5703,7 +5716,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       bu32 fg = DREG (src0);
       bu32 bg = DREG (src1);
       bu32 len = fg & 0x1f;
-      bu32 mask = (1 << MIN (16, len)) - 1;
+      bu32 mask = (1 << min (16, len)) - 1;
       bu32 fgnd = (fg >> 16) & mask;
       int shft = ((fg >> 8) & 0x1f);
 
@@ -6070,7 +6083,11 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       int count = imm6 (immag);
 
       TRACE_INSN (cpu, "R%i = R%i << %i (S);", dst0, src1, count);
-      STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1));
+
+      if (count < 0)
+       STORE (DREG (dst0), ashiftrt (cpu, DREG (src1), -count, 32));
+      else
+       STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1));
     }
   else if (sop == 2 && sopcde == 2)
     {